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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\TangPrimer-25K-example\hdmi\svo\impl\gwsynthesis\hdmi.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>F:\TangPrimer-25K-example\hdmi\svo\src\hdmi.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>F:\TangPrimer-25K-example\hdmi\svo\src\hdmi.sdc</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-3</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Aug 31 10:33:13 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.85V -40C ES</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 0.95V 100C ES</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>7291</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>3661</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>9</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>944</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk_50</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>clk </td>
</tr>
<tr>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Generated</td>
<td>1.176</td>
<td>850.000
<td>0.000</td>
<td>0.588</td>
<td>clk_ibuf/I</td>
<td>clk_50</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0 </td>
</tr>
<tr>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>5.882</td>
<td>170.000
<td>0.000</td>
<td>2.941</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk_50</td>
<td>50.000(MHz)</td>
<td>424.412(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>170.000(MHz)</td>
<td style="color: #FF0000;" class = "error">74.320(MHz)</td>
<td>18</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk_50</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk_50</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>-1473.051</td>
<td>911</td>
</tr>
<tr>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-7.573</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_7_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.027</td>
<td>13.367</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-7.421</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_5_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.016</td>
<td>13.226</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-7.267</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_4_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.018</td>
<td>13.070</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-7.120</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_6_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.020</td>
<td>12.920</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-7.028</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_7_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.016</td>
<td>12.833</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-6.991</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>-0.014</td>
<td>12.826</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-6.987</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_5_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>-0.007</td>
<td>12.815</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>8</td>
<td>-6.986</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_4_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>-0.014</td>
<td>12.821</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>9</td>
<td>-6.842</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.058</td>
<td>12.605</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>10</td>
<td>-6.797</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_1_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.020</td>
<td>12.599</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>11</td>
<td>-6.778</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_5_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.002</td>
<td>12.596</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>12</td>
<td>-6.657</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_1_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.030</td>
<td>12.449</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>13</td>
<td>-6.538</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_3_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.010</td>
<td>12.349</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>14</td>
<td>-6.538</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_9_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.010</td>
<td>12.349</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>15</td>
<td>-6.537</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_4_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.009</td>
<td>12.349</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>16</td>
<td>-6.532</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_7_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.032</td>
<td>12.320</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>17</td>
<td>-6.524</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_3_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.011</td>
<td>12.334</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>18</td>
<td>-6.410</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_4_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.043</td>
<td>12.188</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>19</td>
<td>-6.390</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_6_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>-0.023</td>
<td>12.234</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>20</td>
<td>-6.372</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_1_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_4_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.002</td>
<td>12.192</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>21</td>
<td>-6.323</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_6_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.048</td>
<td>12.096</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>22</td>
<td>-6.293</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_6_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.049</td>
<td>12.065</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>23</td>
<td>-6.269</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_2_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>-0.007</td>
<td>12.097</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>24</td>
<td>-6.257</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_5_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.043</td>
<td>12.036</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>25</td>
<td>-6.247</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_0_s0/D</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.036</td>
<td>12.032</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.223</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_9_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8/DI[1]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.002</td>
<td>0.286</td>
</tr>
<tr>
<td>2</td>
<td>0.224</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_2_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/DI[2]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.002</td>
<td>0.286</td>
</tr>
<tr>
<td>3</td>
<td>0.224</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_3_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/DI[3]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.002</td>
<td>0.286</td>
</tr>
<tr>
<td>4</td>
<td>0.228</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_1_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/DI[1]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.002</td>
<td>0.286</td>
</tr>
<tr>
<td>5</td>
<td>0.230</td>
<td>svo_hdmi_inst_0/svo_tmds_1/q_out_3_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s4/DI[3]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.005</td>
<td>0.286</td>
</tr>
<tr>
<td>6</td>
<td>0.230</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_4_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6/DI[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.005</td>
<td>0.286</td>
</tr>
<tr>
<td>7</td>
<td>0.230</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_3_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/DI[3]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.005</td>
<td>0.286</td>
</tr>
<tr>
<td>8</td>
<td>0.230</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_0_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/DI[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.005</td>
<td>0.286</td>
</tr>
<tr>
<td>9</td>
<td>0.235</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s2/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s4/AD[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.002</td>
<td>0.293</td>
</tr>
<tr>
<td>10</td>
<td>0.241</td>
<td>svo_hdmi_inst_1/svo_tmds_2/q_out_3_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4/DI[3]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.010</td>
<td>0.292</td>
</tr>
<tr>
<td>11</td>
<td>0.242</td>
<td>svo_hdmi_inst_2/svo_enc/ctrl_fifo_rdaddr_1_s0/Q</td>
<td>svo_hdmi_inst_2/svo_enc/out_fifo_out_fifo_0_0_s/WAD[1]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.002</td>
<td>0.304</td>
</tr>
<tr>
<td>12</td>
<td>0.317</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_8_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8/DI[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.004</td>
<td>0.382</td>
</tr>
<tr>
<td>13</td>
<td>0.317</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_6_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6/DI[2]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.004</td>
<td>0.382</td>
</tr>
<tr>
<td>14</td>
<td>0.322</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_8_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s8/DI[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.382</td>
</tr>
<tr>
<td>15</td>
<td>0.322</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_1_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s4/DI[1]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.382</td>
</tr>
<tr>
<td>16</td>
<td>0.328</td>
<td>svo_hdmi_inst_2/svo_tmds_2/q_out_8_s0/Q</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s8/DI[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.013</td>
<td>0.401</td>
</tr>
<tr>
<td>17</td>
<td>0.329</td>
<td>svo_hdmi_inst_1/svo_tmds_1/q_out_5_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s6/DI[1]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.012</td>
<td>0.401</td>
</tr>
<tr>
<td>18</td>
<td>0.331</td>
<td>svo_hdmi_inst_0/svo_tmds_1/q_out_7_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s6/DI[3]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.010</td>
<td>0.382</td>
</tr>
<tr>
<td>19</td>
<td>0.331</td>
<td>svo_hdmi_inst_1/svo_tmds_2/q_out_2_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4/DI[2]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.010</td>
<td>0.382</td>
</tr>
<tr>
<td>20</td>
<td>0.334</td>
<td>svo_hdmi_inst_1/svo_tmds_1/q_out_3_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s4/DI[3]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.007</td>
<td>0.401</td>
</tr>
<tr>
<td>21</td>
<td>0.334</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_2_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/DI[2]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.007</td>
<td>0.401</td>
</tr>
<tr>
<td>22</td>
<td>0.334</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_0_s0/Q</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/DI[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.007</td>
<td>0.401</td>
</tr>
<tr>
<td>23</td>
<td>0.335</td>
<td>svo_hdmi_inst_0/svo_enc/ctrl_fifo_rdaddr_1_s0/Q</td>
<td>svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s/WAD[1]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.006</td>
<td>0.401</td>
</tr>
<tr>
<td>24</td>
<td>0.336</td>
<td>svo_hdmi_inst_0/svo_enc/ctrl_fifo_rdaddr_0_s2/Q</td>
<td>svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s/WAD[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.006</td>
<td>0.402</td>
</tr>
<tr>
<td>25</td>
<td>0.336</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_8_s0/Q</td>
<td>svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s8/DI[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.005</td>
<td>0.401</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-3.618</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-3.618</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-3.618</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-3.618</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-3.618</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-3.613</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.608</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-3.584</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.579</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>8</td>
<td>-3.579</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.574</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>9</td>
<td>-3.571</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_0/tmds_serdes[0]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
<td>0.588</td>
<td>-0.593</td>
<td>4.566</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>10</td>
<td>-3.032</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>1.176</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>11</td>
<td>-3.032</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>1.176</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>12</td>
<td>-3.032</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>1.176</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>13</td>
<td>-3.032</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>1.176</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>14</td>
<td>-3.032</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>1.176</td>
<td>-0.593</td>
<td>4.613</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>15</td>
<td>-3.026</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>1.176</td>
<td>-0.593</td>
<td>4.608</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>16</td>
<td>-2.998</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>1.176</td>
<td>-0.593</td>
<td>4.579</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>17</td>
<td>-2.993</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>1.176</td>
<td>-0.593</td>
<td>4.574</td>
</tr>
<tr>
<td>18</td>
<td>0.937</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.179</td>
<td>4.613</td>
</tr>
<tr>
<td>19</td>
<td>0.946</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.170</td>
<td>4.613</td>
</tr>
<tr>
<td>20</td>
<td>0.946</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.170</td>
<td>4.613</td>
</tr>
<tr>
<td>21</td>
<td>0.946</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.170</td>
<td>4.613</td>
</tr>
<tr>
<td>22</td>
<td>0.946</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.170</td>
<td>4.613</td>
</tr>
<tr>
<td>23</td>
<td>1.150</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>0.005</td>
<td>4.574</td>
</tr>
<tr>
<td>24</td>
<td>1.152</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>-0.031</td>
<td>4.608</td>
</tr>
<tr>
<td>25</td>
<td>1.158</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>5.882</td>
<td>-0.007</td>
<td>4.579</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.577</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_7_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.685</td>
<td>1.116</td>
</tr>
<tr>
<td>2</td>
<td>0.577</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_8_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.685</td>
<td>1.116</td>
</tr>
<tr>
<td>3</td>
<td>0.577</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_9_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.685</td>
<td>1.116</td>
</tr>
<tr>
<td>4</td>
<td>0.577</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_10_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.685</td>
<td>1.116</td>
</tr>
<tr>
<td>5</td>
<td>0.577</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_11_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.685</td>
<td>1.116</td>
</tr>
<tr>
<td>6</td>
<td>0.577</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_12_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.685</td>
<td>1.116</td>
</tr>
<tr>
<td>7</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_0_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>8</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_1_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>9</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_2_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>10</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_3_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>11</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_4_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>12</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_5_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>13</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_6_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>14</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_13_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>15</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_14_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>16</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_15_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>17</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_16_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>18</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_17_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>19</td>
<td>0.582</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_18_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.680</td>
<td>1.116</td>
</tr>
<tr>
<td>20</td>
<td>0.587</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_23_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.675</td>
<td>1.116</td>
</tr>
<tr>
<td>21</td>
<td>0.587</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_19_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.675</td>
<td>1.116</td>
</tr>
<tr>
<td>22</td>
<td>0.587</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_20_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.675</td>
<td>1.116</td>
</tr>
<tr>
<td>23</td>
<td>0.587</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_21_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.675</td>
<td>1.116</td>
</tr>
<tr>
<td>24</td>
<td>0.587</td>
<td>u_Reset_Sync/reset_cnt_3_s0/Q</td>
<td>led_cnt_22_s0/CLEAR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>clk_50:[R]</td>
<td>-0.000</td>
<td>-0.675</td>
<td>1.116</td>
</tr>
<tr>
<td>25</td>
<td>1.727</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst_0/tmds_serdes[0]/RESET</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.763</td>
<td>2.678</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>1.767</td>
<td>2.767</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>svo_hdmi_inst_2/svo_tcard/vdma_tdata_0_s135</td>
</tr>
<tr>
<td>2</td>
<td>1.770</td>
<td>2.770</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>svo_hdmi_inst_2/svo_tcard/vdma_tdata_0_s135</td>
</tr>
<tr>
<td>3</td>
<td>1.772</td>
<td>2.772</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>svo_hdmi_inst_0/svo_tcard/vdma_tdata_0_s135</td>
</tr>
<tr>
<td>4</td>
<td>1.772</td>
<td>2.772</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>svo_hdmi_inst_1/svo_tcard/vdma_tdata_0_s135</td>
</tr>
<tr>
<td>5</td>
<td>1.774</td>
<td>2.774</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>svo_hdmi_inst_0/svo_tcard/vdma_tdata_0_s135</td>
</tr>
<tr>
<td>6</td>
<td>1.774</td>
<td>2.774</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>svo_hdmi_inst_1/svo_tcard/vdma_tdata_0_s135</td>
</tr>
<tr>
<td>7</td>
<td>10000000000.000</td>
<td>9.833</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk_50</td>
<td>led_cnt_21_s0</td>
</tr>
<tr>
<td>8</td>
<td>10000000000.000</td>
<td>9.833</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk_50</td>
<td>led_cnt_19_s0</td>
</tr>
<tr>
<td>9</td>
<td>10000000000.000</td>
<td>9.829</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk_50</td>
<td>led_cnt_15_s0</td>
</tr>
<tr>
<td>10</td>
<td>10000000000.000</td>
<td>9.825</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk_50</td>
<td>led_cnt_7_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.573</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.748</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.175</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.381</td>
<td>0.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/CLK</td>
</tr>
<tr>
<td>0.748</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R24C47[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
</tr>
<tr>
<td>2.392</td>
<td>1.644</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n407_s3/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C45[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>3.065</td>
<td>0.168</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n404_s3/I3</td>
</tr>
<tr>
<td>3.317</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R11C44[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n404_s3/F</td>
</tr>
<tr>
<td>3.845</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s4/I3</td>
</tr>
<tr>
<td>4.351</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R9C44[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>4.508</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s3/I0</td>
</tr>
<tr>
<td>4.951</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>5.104</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>5.547</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>6.215</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s14/I2</td>
</tr>
<tr>
<td>6.711</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s14/F</td>
</tr>
<tr>
<td>6.875</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s10/I3</td>
</tr>
<tr>
<td>7.381</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>8.092</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C45[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>8.371</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R7C45[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>8.493</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C45[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n245_s/I1</td>
</tr>
<tr>
<td>8.966</td>
<td>0.473</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C45[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n245_s/COUT</td>
</tr>
<tr>
<td>8.966</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s/CIN</td>
</tr>
<tr>
<td>9.250</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s/SUM</td>
</tr>
<tr>
<td>9.651</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C46[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s0/I0</td>
</tr>
<tr>
<td>10.185</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C46[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s0/COUT</td>
</tr>
<tr>
<td>10.185</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C46[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n325_s0/CIN</td>
</tr>
<tr>
<td>10.233</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C46[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n325_s0/COUT</td>
</tr>
<tr>
<td>10.233</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n324_s0/CIN</td>
</tr>
<tr>
<td>10.467</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R7C47[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n324_s0/SUM</td>
</tr>
<tr>
<td>11.360</td>
<td>0.893</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C43[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n378_s5/I0</td>
</tr>
<tr>
<td>11.855</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R7C43[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n378_s5/F</td>
</tr>
<tr>
<td>11.866</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C43[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n377_s5/I3</td>
</tr>
<tr>
<td>12.362</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C43[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n377_s5/F</td>
</tr>
<tr>
<td>12.365</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C43[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n377_s3/I0</td>
</tr>
<tr>
<td>12.843</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C43[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n377_s3/F</td>
</tr>
<tr>
<td>12.997</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C43[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n377_s1/I0</td>
</tr>
<tr>
<td>13.249</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R8C43[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n377_s1/F</td>
</tr>
<tr>
<td>13.252</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C43[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n377_s0/I0</td>
</tr>
<tr>
<td>13.748</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R8C43[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n377_s0/F</td>
</tr>
<tr>
<td>13.748</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C43[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.236</td>
<td>0.354</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C43[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.175</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C43[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.027</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.381, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.217, 53.990%; route: 5.783, 43.262%; tC2Q: 0.367, 2.747%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.354, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.421</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.607</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.187</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.381</td>
<td>0.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/CLK</td>
</tr>
<tr>
<td>0.748</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R24C47[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
</tr>
<tr>
<td>2.392</td>
<td>1.644</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n407_s3/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C45[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>3.065</td>
<td>0.168</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n404_s3/I3</td>
</tr>
<tr>
<td>3.317</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R11C44[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n404_s3/F</td>
</tr>
<tr>
<td>3.845</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s4/I3</td>
</tr>
<tr>
<td>4.351</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R9C44[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>4.508</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s3/I0</td>
</tr>
<tr>
<td>4.951</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>5.104</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>5.547</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>6.215</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s14/I2</td>
</tr>
<tr>
<td>6.711</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s14/F</td>
</tr>
<tr>
<td>6.875</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s10/I3</td>
</tr>
<tr>
<td>7.381</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>8.092</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C45[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>8.371</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R7C45[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>8.493</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C45[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n245_s/I1</td>
</tr>
<tr>
<td>8.966</td>
<td>0.473</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C45[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n245_s/COUT</td>
</tr>
<tr>
<td>8.966</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s/CIN</td>
</tr>
<tr>
<td>9.014</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s/COUT</td>
</tr>
<tr>
<td>9.014</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C45[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n325_s/CIN</td>
</tr>
<tr>
<td>9.062</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C45[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n325_s/COUT</td>
</tr>
<tr>
<td>9.062</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C45[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n324_s/CIN</td>
</tr>
<tr>
<td>9.346</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C45[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n324_s/SUM</td>
</tr>
<tr>
<td>10.010</td>
<td>0.664</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n324_s0/I0</td>
</tr>
<tr>
<td>10.544</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C47[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n324_s0/COUT</td>
</tr>
<tr>
<td>10.544</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C47[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n323_s0/CIN</td>
</tr>
<tr>
<td>10.828</td>
<td>0.284</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R7C47[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n323_s0/SUM</td>
</tr>
<tr>
<td>12.237</td>
<td>1.409</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n379_s3/I0</td>
</tr>
<tr>
<td>12.680</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n379_s3/F</td>
</tr>
<tr>
<td>12.683</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n379_s1/I0</td>
</tr>
<tr>
<td>13.161</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R5C43[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n379_s1/F</td>
</tr>
<tr>
<td>13.165</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n379_s0/I0</td>
</tr>
<tr>
<td>13.607</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R5C43[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n379_s0/F</td>
</tr>
<tr>
<td>13.607</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.248</td>
<td>0.365</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_5_s0/CLK</td>
</tr>
<tr>
<td>6.187</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C43[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.016</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.381, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.462, 48.857%; route: 6.397, 48.367%; tC2Q: 0.367, 2.776%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.365, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.267</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.451</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.184</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.381</td>
<td>0.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/CLK</td>
</tr>
<tr>
<td>0.748</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R24C47[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
</tr>
<tr>
<td>2.392</td>
<td>1.644</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n407_s3/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C45[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>3.065</td>
<td>0.168</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n404_s3/I3</td>
</tr>
<tr>
<td>3.317</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R11C44[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n404_s3/F</td>
</tr>
<tr>
<td>3.845</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s4/I3</td>
</tr>
<tr>
<td>4.351</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R9C44[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>4.508</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s3/I0</td>
</tr>
<tr>
<td>4.951</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>5.104</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>5.547</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>6.215</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s14/I2</td>
</tr>
<tr>
<td>6.711</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s14/F</td>
</tr>
<tr>
<td>6.875</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s10/I3</td>
</tr>
<tr>
<td>7.381</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>8.092</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C45[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>8.371</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R7C45[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>8.493</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C45[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n245_s/I1</td>
</tr>
<tr>
<td>8.966</td>
<td>0.473</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C45[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n245_s/COUT</td>
</tr>
<tr>
<td>8.966</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s/CIN</td>
</tr>
<tr>
<td>9.250</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s/SUM</td>
</tr>
<tr>
<td>9.651</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C46[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s0/I0</td>
</tr>
<tr>
<td>10.185</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C46[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s0/COUT</td>
</tr>
<tr>
<td>10.185</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C46[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n325_s0/CIN</td>
</tr>
<tr>
<td>10.233</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C46[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n325_s0/COUT</td>
</tr>
<tr>
<td>10.233</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n324_s0/CIN</td>
</tr>
<tr>
<td>10.467</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R7C47[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n324_s0/SUM</td>
</tr>
<tr>
<td>11.360</td>
<td>0.893</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C43[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n378_s5/I0</td>
</tr>
<tr>
<td>11.855</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R7C43[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n378_s5/F</td>
</tr>
<tr>
<td>12.051</td>
<td>0.196</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n380_s3/I1</td>
</tr>
<tr>
<td>12.547</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R5C43[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n380_s3/F</td>
</tr>
<tr>
<td>12.550</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n380_s1/I0</td>
</tr>
<tr>
<td>12.802</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R5C43[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n380_s1/F</td>
</tr>
<tr>
<td>12.956</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C43[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n380_s0/I0</td>
</tr>
<tr>
<td>13.451</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R6C43[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n380_s0/F</td>
</tr>
<tr>
<td>13.451</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C43[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.245</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C43[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_4_s0/CLK</td>
</tr>
<tr>
<td>6.184</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C43[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.018</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>17</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.381, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.739, 51.561%; route: 5.964, 45.630%; tC2Q: 0.367, 2.809%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.363, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.120</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.301</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.381</td>
<td>0.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/CLK</td>
</tr>
<tr>
<td>0.748</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R24C47[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
</tr>
<tr>
<td>2.392</td>
<td>1.644</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n407_s3/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C45[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>3.065</td>
<td>0.168</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n404_s3/I3</td>
</tr>
<tr>
<td>3.317</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R11C44[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n404_s3/F</td>
</tr>
<tr>
<td>3.845</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s4/I3</td>
</tr>
<tr>
<td>4.351</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R9C44[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>4.508</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s3/I0</td>
</tr>
<tr>
<td>4.951</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>5.104</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>5.547</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>6.215</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s14/I2</td>
</tr>
<tr>
<td>6.711</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s14/F</td>
</tr>
<tr>
<td>6.875</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s10/I3</td>
</tr>
<tr>
<td>7.381</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>8.092</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C45[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>8.371</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R7C45[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>8.493</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C45[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n245_s/I1</td>
</tr>
<tr>
<td>8.966</td>
<td>0.473</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C45[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n245_s/COUT</td>
</tr>
<tr>
<td>8.966</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s/CIN</td>
</tr>
<tr>
<td>9.250</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s/SUM</td>
</tr>
<tr>
<td>9.651</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C46[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s0/I0</td>
</tr>
<tr>
<td>10.185</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C46[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s0/COUT</td>
</tr>
<tr>
<td>10.185</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C46[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n325_s0/CIN</td>
</tr>
<tr>
<td>10.233</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C46[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n325_s0/COUT</td>
</tr>
<tr>
<td>10.233</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n324_s0/CIN</td>
</tr>
<tr>
<td>10.467</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R7C47[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n324_s0/SUM</td>
</tr>
<tr>
<td>11.360</td>
<td>0.893</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C43[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n378_s5/I0</td>
</tr>
<tr>
<td>11.855</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R7C43[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n378_s5/F</td>
</tr>
<tr>
<td>12.016</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C44[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n378_s3/I2</td>
</tr>
<tr>
<td>12.494</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C44[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n378_s3/F</td>
</tr>
<tr>
<td>12.497</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C44[3][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n378_s1/I0</td>
</tr>
<tr>
<td>12.896</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C44[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n378_s1/F</td>
</tr>
<tr>
<td>13.049</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C43[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n378_s0/I0</td>
</tr>
<tr>
<td>13.301</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C43[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n378_s0/F</td>
</tr>
<tr>
<td>13.301</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C43[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.243</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C43[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_6_s0/CLK</td>
</tr>
<tr>
<td>6.182</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C43[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.020</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>17</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.381, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.624, 51.268%; route: 5.929, 45.890%; tC2Q: 0.367, 2.842%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.361, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.028</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.205</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.177</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.372</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C48[1][B]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/CLK</td>
</tr>
<tr>
<td>0.739</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R24C48[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/Q</td>
</tr>
<tr>
<td>2.734</td>
<td>1.994</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[3][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n407_s3/I2</td>
</tr>
<tr>
<td>3.132</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R4C48[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.538</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C51[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n404_s3/I3</td>
</tr>
<tr>
<td>4.068</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R6C51[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n404_s3/F</td>
</tr>
<tr>
<td>4.415</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s2/I1</td>
</tr>
<tr>
<td>4.920</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R6C48[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>4.927</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>5.179</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R6C48[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>5.314</td>
<td>0.134</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>5.712</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R6C48[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>6.062</td>
<td>0.350</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n175_s17/I1</td>
</tr>
<tr>
<td>6.568</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R4C48[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n175_s17/F</td>
</tr>
<tr>
<td>7.223</td>
<td>0.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n174_s16/I3</td>
</tr>
<tr>
<td>7.728</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R6C49[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n174_s16/F</td>
</tr>
<tr>
<td>7.739</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n174_s15/I0</td>
</tr>
<tr>
<td>8.137</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R6C49[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n174_s15/F</td>
</tr>
<tr>
<td>8.663</td>
<td>0.526</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C50[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n325_s/I1</td>
</tr>
<tr>
<td>9.210</td>
<td>0.547</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C50[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n325_s/SUM</td>
</tr>
<tr>
<td>9.527</td>
<td>0.317</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C51[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n325_s0/I0</td>
</tr>
<tr>
<td>10.061</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C51[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n325_s0/COUT</td>
</tr>
<tr>
<td>10.061</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C52[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n324_s0/CIN</td>
</tr>
<tr>
<td>10.295</td>
<td>0.234</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C52[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n324_s0/SUM</td>
</tr>
<tr>
<td>10.675</td>
<td>0.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C49[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n378_s5/I0</td>
</tr>
<tr>
<td>11.171</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R9C49[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n378_s5/F</td>
</tr>
<tr>
<td>11.335</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C48[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n377_s5/I3</td>
</tr>
<tr>
<td>11.831</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C48[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n377_s5/F</td>
</tr>
<tr>
<td>11.834</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C48[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n377_s3/I0</td>
</tr>
<tr>
<td>12.277</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C48[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n377_s3/F</td>
</tr>
<tr>
<td>12.281</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C48[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n377_s1/I0</td>
</tr>
<tr>
<td>12.758</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C48[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n377_s1/F</td>
</tr>
<tr>
<td>12.762</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n377_s0/I0</td>
</tr>
<tr>
<td>13.205</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C48[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n377_s0/F</td>
</tr>
<tr>
<td>13.205</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C48[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.238</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.177</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.016</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>17</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.372, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.031, 54.788%; route: 5.435, 42.351%; tC2Q: 0.367, 2.861%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.356, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.991</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.172</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.347</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/CLK</td>
</tr>
<tr>
<td>0.714</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R27C33[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
</tr>
<tr>
<td>2.359</td>
<td>1.645</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n407_s3/I3</td>
</tr>
<tr>
<td>2.611</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R29C28[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>2.622</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s4/I2</td>
</tr>
<tr>
<td>3.020</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C28[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s4/F</td>
</tr>
<tr>
<td>3.178</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s2/I2</td>
</tr>
<tr>
<td>3.673</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>3.680</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>3.932</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>4.586</td>
<td>0.654</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>5.029</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R27C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.547</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s13/I3</td>
</tr>
<tr>
<td>6.082</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s13/F</td>
</tr>
<tr>
<td>6.096</td>
<td>0.014</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s10/I2</td>
</tr>
<tr>
<td>6.539</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s10/F</td>
</tr>
<tr>
<td>6.882</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n176_s13/I0</td>
</tr>
<tr>
<td>7.360</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R26C24[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n176_s13/F</td>
</tr>
<tr>
<td>8.174</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n223_s/I1</td>
</tr>
<tr>
<td>8.647</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n223_s/COUT</td>
</tr>
<tr>
<td>8.647</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n289_s/CIN</td>
</tr>
<tr>
<td>8.695</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n289_s/COUT</td>
</tr>
<tr>
<td>8.695</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s/CIN</td>
</tr>
<tr>
<td>8.929</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s/SUM</td>
</tr>
<tr>
<td>9.733</td>
<td>0.804</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R27C25[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s0/I0</td>
</tr>
<tr>
<td>10.267</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R27C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s0/COUT</td>
</tr>
<tr>
<td>10.267</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R27C26[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n287_s0/CIN</td>
</tr>
<tr>
<td>10.501</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R27C26[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n287_s0/SUM</td>
</tr>
<tr>
<td>11.005</td>
<td>0.504</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C25[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s6/I3</td>
</tr>
<tr>
<td>11.404</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C25[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n378_s6/F</td>
</tr>
<tr>
<td>11.564</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s6/I3</td>
</tr>
<tr>
<td>11.816</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C24[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n377_s6/F</td>
</tr>
<tr>
<td>11.970</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s4/I0</td>
</tr>
<tr>
<td>12.222</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C23[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n377_s4/F</td>
</tr>
<tr>
<td>12.226</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s1/I1</td>
</tr>
<tr>
<td>12.726</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C23[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n377_s1/F</td>
</tr>
<tr>
<td>12.730</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n377_s0/I0</td>
</tr>
<tr>
<td>13.172</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C23[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n377_s0/F</td>
</tr>
<tr>
<td>13.172</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.243</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.182</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C23[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.635, 51.731%; route: 5.824, 45.406%; tC2Q: 0.367, 2.863%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.361, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.987</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.162</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.175</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.347</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/CLK</td>
</tr>
<tr>
<td>0.714</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R27C33[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
</tr>
<tr>
<td>2.359</td>
<td>1.645</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n407_s3/I3</td>
</tr>
<tr>
<td>2.611</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R29C28[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>2.622</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s4/I2</td>
</tr>
<tr>
<td>3.020</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C28[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s4/F</td>
</tr>
<tr>
<td>3.178</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s2/I2</td>
</tr>
<tr>
<td>3.673</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>3.680</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>3.932</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>4.586</td>
<td>0.654</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>5.029</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R27C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.547</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s13/I3</td>
</tr>
<tr>
<td>6.082</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s13/F</td>
</tr>
<tr>
<td>6.096</td>
<td>0.014</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s10/I2</td>
</tr>
<tr>
<td>6.539</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s10/F</td>
</tr>
<tr>
<td>6.882</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n176_s13/I0</td>
</tr>
<tr>
<td>7.360</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R26C24[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n176_s13/F</td>
</tr>
<tr>
<td>8.174</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n223_s/I1</td>
</tr>
<tr>
<td>8.647</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n223_s/COUT</td>
</tr>
<tr>
<td>8.647</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n289_s/CIN</td>
</tr>
<tr>
<td>8.695</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n289_s/COUT</td>
</tr>
<tr>
<td>8.695</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s/CIN</td>
</tr>
<tr>
<td>8.929</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s/SUM</td>
</tr>
<tr>
<td>9.733</td>
<td>0.804</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R27C25[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s0/I0</td>
</tr>
<tr>
<td>10.267</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R27C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s0/COUT</td>
</tr>
<tr>
<td>10.267</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R27C26[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n287_s0/CIN</td>
</tr>
<tr>
<td>10.501</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R27C26[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n287_s0/SUM</td>
</tr>
<tr>
<td>11.005</td>
<td>0.504</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C25[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s6/I3</td>
</tr>
<tr>
<td>11.404</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C25[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n378_s6/F</td>
</tr>
<tr>
<td>11.564</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n379_s4/I1</td>
</tr>
<tr>
<td>11.816</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C24[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n379_s4/F</td>
</tr>
<tr>
<td>11.820</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n379_s1/I1</td>
</tr>
<tr>
<td>12.320</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C24[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n379_s1/F</td>
</tr>
<tr>
<td>12.656</td>
<td>0.336</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n379_s0/I0</td>
</tr>
<tr>
<td>13.162</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C23[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n379_s0/F</td>
</tr>
<tr>
<td>13.162</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.236</td>
<td>0.354</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_5_s0/CLK</td>
</tr>
<tr>
<td>6.175</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C23[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.007</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>17</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.445, 50.295%; route: 6.002, 46.840%; tC2Q: 0.367, 2.865%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.354, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.986</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.168</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.347</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/CLK</td>
</tr>
<tr>
<td>0.714</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R27C33[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
</tr>
<tr>
<td>2.359</td>
<td>1.645</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n407_s3/I3</td>
</tr>
<tr>
<td>2.611</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R29C28[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>2.622</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s4/I2</td>
</tr>
<tr>
<td>3.020</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C28[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s4/F</td>
</tr>
<tr>
<td>3.178</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s2/I2</td>
</tr>
<tr>
<td>3.673</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>3.680</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>3.932</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>4.586</td>
<td>0.654</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>5.029</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R27C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.547</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s13/I3</td>
</tr>
<tr>
<td>6.082</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s13/F</td>
</tr>
<tr>
<td>6.096</td>
<td>0.014</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s10/I2</td>
</tr>
<tr>
<td>6.539</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s10/F</td>
</tr>
<tr>
<td>6.882</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n176_s13/I0</td>
</tr>
<tr>
<td>7.360</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R26C24[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n176_s13/F</td>
</tr>
<tr>
<td>8.174</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n223_s/I1</td>
</tr>
<tr>
<td>8.647</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n223_s/COUT</td>
</tr>
<tr>
<td>8.647</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n289_s/CIN</td>
</tr>
<tr>
<td>8.695</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n289_s/COUT</td>
</tr>
<tr>
<td>8.695</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s/CIN</td>
</tr>
<tr>
<td>8.929</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s/SUM</td>
</tr>
<tr>
<td>9.733</td>
<td>0.804</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R27C25[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s0/I0</td>
</tr>
<tr>
<td>10.267</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R27C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s0/COUT</td>
</tr>
<tr>
<td>10.267</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R27C26[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n287_s0/CIN</td>
</tr>
<tr>
<td>10.501</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R27C26[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n287_s0/SUM</td>
</tr>
<tr>
<td>11.005</td>
<td>0.504</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C25[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s6/I3</td>
</tr>
<tr>
<td>11.404</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C25[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n378_s6/F</td>
</tr>
<tr>
<td>11.557</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n380_s4/I1</td>
</tr>
<tr>
<td>12.000</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C26[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n380_s4/F</td>
</tr>
<tr>
<td>12.154</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n380_s1/I1</td>
</tr>
<tr>
<td>12.659</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C27[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n380_s1/F</td>
</tr>
<tr>
<td>12.662</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n380_s0/I0</td>
</tr>
<tr>
<td>13.168</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n380_s0/F</td>
</tr>
<tr>
<td>13.168</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.243</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_4_s0/CLK</td>
</tr>
<tr>
<td>6.182</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>17</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.641, 51.797%; route: 5.813, 45.339%; tC2Q: 0.367, 2.864%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.361, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.842</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.977</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.135</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.372</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/CLK</td>
</tr>
<tr>
<td>0.739</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R24C44[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/Q</td>
</tr>
<tr>
<td>1.782</td>
<td>1.043</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C50[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s6/I2</td>
</tr>
<tr>
<td>2.225</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R22C50[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.232</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C50[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s5/I2</td>
</tr>
<tr>
<td>2.728</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R22C50[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s5/F</td>
</tr>
<tr>
<td>2.917</td>
<td>0.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C50[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s3/I3</td>
</tr>
<tr>
<td>3.360</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C50[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s3/F</td>
</tr>
<tr>
<td>3.494</td>
<td>0.134</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C50[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s0/I3</td>
</tr>
<tr>
<td>3.893</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>32</td>
<td>R21C50[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>5.480</td>
<td>1.588</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C52[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n175_s16/I3</td>
</tr>
<tr>
<td>5.976</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R20C52[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n175_s16/F</td>
</tr>
<tr>
<td>6.632</td>
<td>0.656</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C52[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n260_s2/I1</td>
</tr>
<tr>
<td>7.138</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C52[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n260_s2/F</td>
</tr>
<tr>
<td>7.512</td>
<td>0.374</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C52[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n174_s15/I1</td>
</tr>
<tr>
<td>7.955</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R14C52[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n174_s15/F</td>
</tr>
<tr>
<td>8.116</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R14C51[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n325_s/I1</td>
</tr>
<tr>
<td>8.588</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R14C51[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n325_s/COUT</td>
</tr>
<tr>
<td>8.588</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R14C51[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n324_s/CIN</td>
</tr>
<tr>
<td>8.873</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R14C51[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n324_s/SUM</td>
</tr>
<tr>
<td>9.340</td>
<td>0.467</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R15C51[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n324_s0/I0</td>
</tr>
<tr>
<td>10.042</td>
<td>0.702</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R15C51[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n324_s0/SUM</td>
</tr>
<tr>
<td>10.199</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C51[3][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n378_s5/I0</td>
</tr>
<tr>
<td>10.676</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R14C51[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n378_s5/F</td>
</tr>
<tr>
<td>11.022</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s5/I3</td>
</tr>
<tr>
<td>11.500</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C52[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n377_s5/F</td>
</tr>
<tr>
<td>11.503</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s3/I0</td>
</tr>
<tr>
<td>11.946</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C52[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n377_s3/F</td>
</tr>
<tr>
<td>12.132</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C50[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s1/I0</td>
</tr>
<tr>
<td>12.530</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C50[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n377_s1/F</td>
</tr>
<tr>
<td>12.534</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C50[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n377_s0/I0</td>
</tr>
<tr>
<td>12.977</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C50[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n377_s0/F</td>
</tr>
<tr>
<td>12.977</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C50[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.196</td>
<td>0.314</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C50[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.135</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C50[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.058</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.372, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.922, 54.912%; route: 5.316, 42.174%; tC2Q: 0.367, 2.913%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.314, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.797</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.944</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.146</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.345</td>
<td>0.345</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C30[0][B]</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_1_s0/CLK</td>
</tr>
<tr>
<td>0.698</td>
<td>0.353</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R8C30[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_enc/out_axis_tdata_1_s0/Q</td>
</tr>
<tr>
<td>2.132</td>
<td>1.434</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C23[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n407_s3/I3</td>
</tr>
<tr>
<td>2.627</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R15C23[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>2.792</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C24[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s8/I1</td>
</tr>
<tr>
<td>3.190</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R15C24[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n88_s8/F</td>
</tr>
<tr>
<td>3.354</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C25[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s4/I3</td>
</tr>
<tr>
<td>3.832</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R15C25[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>3.993</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C24[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s3/I0</td>
</tr>
<tr>
<td>4.493</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R15C24[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>4.650</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C25[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>5.146</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>29</td>
<td>R15C25[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>5.692</td>
<td>0.546</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C23[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n146_s13/I3</td>
</tr>
<tr>
<td>6.197</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R15C23[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n146_s13/F</td>
</tr>
<tr>
<td>6.540</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C24[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n146_s10/I2</td>
</tr>
<tr>
<td>6.792</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R16C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>7.164</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C27[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>7.563</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R16C27[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>7.946</td>
<td>0.383</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R17C28[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n223_s/I1</td>
</tr>
<tr>
<td>8.418</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C28[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n223_s/COUT</td>
</tr>
<tr>
<td>8.418</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R17C28[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n289_s/CIN</td>
</tr>
<tr>
<td>8.466</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C28[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n289_s/COUT</td>
</tr>
<tr>
<td>8.466</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R17C28[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n288_s/CIN</td>
</tr>
<tr>
<td>8.514</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C28[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n288_s/COUT</td>
</tr>
<tr>
<td>8.514</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R17C29[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n287_s/CIN</td>
</tr>
<tr>
<td>8.748</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C29[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n287_s/SUM</td>
</tr>
<tr>
<td>9.251</td>
<td>0.503</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C27[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n287_s0/I0</td>
</tr>
<tr>
<td>9.953</td>
<td>0.702</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n287_s0/SUM</td>
</tr>
<tr>
<td>10.276</td>
<td>0.323</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C27[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n378_s6/I3</td>
</tr>
<tr>
<td>10.674</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R16C27[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n378_s6/F</td>
</tr>
<tr>
<td>10.839</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C27[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s6/I3</td>
</tr>
<tr>
<td>11.344</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C27[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n377_s6/F</td>
</tr>
<tr>
<td>11.498</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C26[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s4/I0</td>
</tr>
<tr>
<td>11.993</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C26[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n377_s4/F</td>
</tr>
<tr>
<td>11.997</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C26[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s1/I1</td>
</tr>
<tr>
<td>12.497</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C26[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n377_s1/F</td>
</tr>
<tr>
<td>12.501</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C26[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n377_s0/I0</td>
</tr>
<tr>
<td>12.944</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C26[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n377_s0/F</td>
</tr>
<tr>
<td>12.944</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C26[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.208</td>
<td>0.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C26[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.146</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C26[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.020</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>17</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.345, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.370, 58.501%; route: 4.876, 38.699%; tC2Q: 0.353, 2.800%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.325, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.968</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.191</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.372</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C48[1][B]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/CLK</td>
</tr>
<tr>
<td>0.739</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R24C48[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/Q</td>
</tr>
<tr>
<td>2.734</td>
<td>1.994</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[3][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n407_s3/I2</td>
</tr>
<tr>
<td>3.132</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R4C48[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.538</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C51[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n404_s3/I3</td>
</tr>
<tr>
<td>4.068</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R6C51[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n404_s3/F</td>
</tr>
<tr>
<td>4.415</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s2/I1</td>
</tr>
<tr>
<td>4.920</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R6C48[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>4.927</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>5.179</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R6C48[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>5.314</td>
<td>0.134</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>5.712</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R6C48[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>6.062</td>
<td>0.350</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n175_s17/I1</td>
</tr>
<tr>
<td>6.568</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R4C48[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n175_s17/F</td>
</tr>
<tr>
<td>7.223</td>
<td>0.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n174_s16/I3</td>
</tr>
<tr>
<td>7.728</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R6C49[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n174_s16/F</td>
</tr>
<tr>
<td>7.739</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n174_s15/I0</td>
</tr>
<tr>
<td>8.137</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R6C49[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n174_s15/F</td>
</tr>
<tr>
<td>8.663</td>
<td>0.526</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C50[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n325_s/I1</td>
</tr>
<tr>
<td>9.210</td>
<td>0.547</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C50[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n325_s/SUM</td>
</tr>
<tr>
<td>9.527</td>
<td>0.317</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C51[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n325_s0/I0</td>
</tr>
<tr>
<td>10.061</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C51[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n325_s0/COUT</td>
</tr>
<tr>
<td>10.061</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C52[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n324_s0/CIN</td>
</tr>
<tr>
<td>10.295</td>
<td>0.234</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C52[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n324_s0/SUM</td>
</tr>
<tr>
<td>10.675</td>
<td>0.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C49[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n378_s5/I0</td>
</tr>
<tr>
<td>11.171</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R9C49[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n378_s5/F</td>
</tr>
<tr>
<td>11.518</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C48[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n379_s3/I1</td>
</tr>
<tr>
<td>12.023</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C48[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n379_s3/F</td>
</tr>
<tr>
<td>12.026</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C48[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n379_s1/I0</td>
</tr>
<tr>
<td>12.522</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C48[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n379_s1/F</td>
</tr>
<tr>
<td>12.526</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n379_s0/I0</td>
</tr>
<tr>
<td>12.968</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C48[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n379_s0/F</td>
</tr>
<tr>
<td>12.968</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C48[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.252</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_5_s0/CLK</td>
</tr>
<tr>
<td>6.191</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.372, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.616, 52.520%; route: 5.614, 44.565%; tC2Q: 0.367, 2.915%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.657</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.796</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.138</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.347</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C31[0][B]</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_1_s0/CLK</td>
</tr>
<tr>
<td>0.714</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R27C31[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/out_axis_tdata_1_s0/Q</td>
</tr>
<tr>
<td>1.922</td>
<td>1.208</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C28[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n407_s3/I3</td>
</tr>
<tr>
<td>2.400</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R30C28[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>2.542</td>
<td>0.142</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C28[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s4/I2</td>
</tr>
<tr>
<td>3.042</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R30C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>3.199</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C27[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s2/I2</td>
</tr>
<tr>
<td>3.704</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R30C27[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n88_s2/F</td>
</tr>
<tr>
<td>3.712</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C27[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s3/I3</td>
</tr>
<tr>
<td>4.207</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R30C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>4.342</td>
<td>0.134</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C27[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>4.784</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R30C27[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>5.164</td>
<td>0.379</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C26[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n146_s12/I0</td>
</tr>
<tr>
<td>5.606</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R31C26[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n146_s12/F</td>
</tr>
<tr>
<td>5.950</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C26[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n146_s10/I1</td>
</tr>
<tr>
<td>6.455</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R33C26[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>6.799</td>
<td>0.344</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C25[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>7.242</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R31C25[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>7.403</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R32C25[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n223_s/I1</td>
</tr>
<tr>
<td>7.876</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R32C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n223_s/COUT</td>
</tr>
<tr>
<td>7.876</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R32C25[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n289_s/CIN</td>
</tr>
<tr>
<td>8.110</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R32C25[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n289_s/SUM</td>
</tr>
<tr>
<td>8.446</td>
<td>0.336</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R33C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n289_s0/I0</td>
</tr>
<tr>
<td>9.148</td>
<td>0.702</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R33C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n289_s0/SUM</td>
</tr>
<tr>
<td>9.655</td>
<td>0.508</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C23[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n378_s6/I2</td>
</tr>
<tr>
<td>10.133</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R31C23[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n378_s6/F</td>
</tr>
<tr>
<td>10.658</td>
<td>0.526</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C25[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s6/I3</td>
</tr>
<tr>
<td>11.101</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R30C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n377_s6/F</td>
</tr>
<tr>
<td>11.287</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C23[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s4/I0</td>
</tr>
<tr>
<td>11.783</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R30C23[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n377_s4/F</td>
</tr>
<tr>
<td>11.786</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C23[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s1/I1</td>
</tr>
<tr>
<td>12.287</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R30C23[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n377_s1/F</td>
</tr>
<tr>
<td>12.290</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C23[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/n377_s0/I0</td>
</tr>
<tr>
<td>12.796</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R30C23[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_2/n377_s0/F</td>
</tr>
<tr>
<td>12.796</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C23[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.199</td>
<td>0.317</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C23[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.138</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C23[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_2/cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.030</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>17</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.643, 61.394%; route: 4.439, 35.656%; tC2Q: 0.367, 2.950%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.317, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.538</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.706</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.168</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.356</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C30[0][B]</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/CLK</td>
</tr>
<tr>
<td>0.724</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R5C30[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
</tr>
<tr>
<td>1.531</td>
<td>0.808</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s6/I3</td>
</tr>
<tr>
<td>2.032</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R9C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.562</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s2/I3</td>
</tr>
<tr>
<td>3.067</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C28[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s2/F</td>
</tr>
<tr>
<td>3.736</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s0/I2</td>
</tr>
<tr>
<td>3.988</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C28[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>6.358</td>
<td>2.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n175_s21/I0</td>
</tr>
<tr>
<td>6.636</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R11C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n175_s21/F</td>
</tr>
<tr>
<td>6.829</td>
<td>0.193</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C26[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n174_s17/I0</td>
</tr>
<tr>
<td>7.334</td>
<td>0.505</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R11C26[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n174_s17/F</td>
</tr>
<tr>
<td>7.679</td>
<td>0.344</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C25[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n173_s11/I1</td>
</tr>
<tr>
<td>8.156</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R12C25[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n173_s11/F</td>
</tr>
<tr>
<td>8.500</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C26[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n181_s0/I0</td>
</tr>
<tr>
<td>9.034</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C26[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n181_s0/COUT</td>
</tr>
<tr>
<td>9.629</td>
<td>0.595</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C24[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n183_s0/I2</td>
</tr>
<tr>
<td>10.124</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>10</td>
<td>R13C24[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n183_s0/F</td>
</tr>
<tr>
<td>10.639</td>
<td>0.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n359_s1/I3</td>
</tr>
<tr>
<td>11.117</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R11C25[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n359_s1/F</td>
</tr>
<tr>
<td>12.200</td>
<td>1.084</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C27[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n407_s0/I1</td>
</tr>
<tr>
<td>12.706</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C27[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n407_s0/F</td>
</tr>
<tr>
<td>12.706</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C27[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/q_out_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.229</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C27[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_3_s0/CLK</td>
</tr>
<tr>
<td>6.168</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C27[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>11</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.356, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.531, 36.692%; route: 7.451, 60.334%; tC2Q: 0.367, 2.973%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.538</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.706</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.168</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.356</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C30[0][B]</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/CLK</td>
</tr>
<tr>
<td>0.724</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R5C30[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
</tr>
<tr>
<td>1.531</td>
<td>0.808</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s6/I3</td>
</tr>
<tr>
<td>2.032</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R9C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.562</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s2/I3</td>
</tr>
<tr>
<td>3.067</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C28[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s2/F</td>
</tr>
<tr>
<td>3.736</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s0/I2</td>
</tr>
<tr>
<td>3.988</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C28[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>6.358</td>
<td>2.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n175_s21/I0</td>
</tr>
<tr>
<td>6.636</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R11C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n175_s21/F</td>
</tr>
<tr>
<td>6.829</td>
<td>0.193</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C26[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n174_s17/I0</td>
</tr>
<tr>
<td>7.334</td>
<td>0.505</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R11C26[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n174_s17/F</td>
</tr>
<tr>
<td>7.679</td>
<td>0.344</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C25[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n173_s11/I1</td>
</tr>
<tr>
<td>8.156</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R12C25[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n173_s11/F</td>
</tr>
<tr>
<td>8.500</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C26[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n181_s0/I0</td>
</tr>
<tr>
<td>9.034</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C26[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n181_s0/COUT</td>
</tr>
<tr>
<td>9.629</td>
<td>0.595</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C24[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n183_s0/I2</td>
</tr>
<tr>
<td>10.124</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>10</td>
<td>R13C24[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n183_s0/F</td>
</tr>
<tr>
<td>10.639</td>
<td>0.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n359_s1/I3</td>
</tr>
<tr>
<td>11.117</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R11C25[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n359_s1/F</td>
</tr>
<tr>
<td>12.200</td>
<td>1.084</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C27[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n401_s0/I0</td>
</tr>
<tr>
<td>12.706</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C27[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n401_s0/F</td>
</tr>
<tr>
<td>12.706</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C27[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/q_out_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.229</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C27[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_9_s0/CLK</td>
</tr>
<tr>
<td>6.168</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C27[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>11</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.356, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.531, 36.692%; route: 7.451, 60.334%; tC2Q: 0.367, 2.973%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.537</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.721</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.184</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.372</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C48[1][B]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/CLK</td>
</tr>
<tr>
<td>0.739</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R24C48[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_11_s0/Q</td>
</tr>
<tr>
<td>2.734</td>
<td>1.994</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[3][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n407_s3/I2</td>
</tr>
<tr>
<td>3.132</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R4C48[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.538</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C51[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n404_s3/I3</td>
</tr>
<tr>
<td>4.068</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R6C51[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n404_s3/F</td>
</tr>
<tr>
<td>4.415</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s2/I1</td>
</tr>
<tr>
<td>4.920</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R6C48[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>4.927</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>5.179</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R6C48[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>5.314</td>
<td>0.134</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>5.712</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R6C48[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>6.062</td>
<td>0.350</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n175_s17/I1</td>
</tr>
<tr>
<td>6.568</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R4C48[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n175_s17/F</td>
</tr>
<tr>
<td>7.223</td>
<td>0.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n174_s16/I3</td>
</tr>
<tr>
<td>7.728</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R6C49[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n174_s16/F</td>
</tr>
<tr>
<td>7.739</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n174_s15/I0</td>
</tr>
<tr>
<td>8.137</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R6C49[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n174_s15/F</td>
</tr>
<tr>
<td>8.663</td>
<td>0.526</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C50[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n325_s/I1</td>
</tr>
<tr>
<td>9.210</td>
<td>0.547</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C50[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n325_s/SUM</td>
</tr>
<tr>
<td>9.527</td>
<td>0.317</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C51[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n325_s0/I0</td>
</tr>
<tr>
<td>10.061</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C51[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n325_s0/COUT</td>
</tr>
<tr>
<td>10.061</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C52[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n324_s0/CIN</td>
</tr>
<tr>
<td>10.295</td>
<td>0.234</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C52[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n324_s0/SUM</td>
</tr>
<tr>
<td>10.675</td>
<td>0.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C49[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n378_s5/I0</td>
</tr>
<tr>
<td>11.171</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R9C49[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n378_s5/F</td>
</tr>
<tr>
<td>11.364</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C49[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n380_s3/I1</td>
</tr>
<tr>
<td>11.807</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C49[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n380_s3/F</td>
</tr>
<tr>
<td>11.960</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n380_s1/I0</td>
</tr>
<tr>
<td>12.466</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R6C49[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n380_s1/F</td>
</tr>
<tr>
<td>12.469</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/n380_s0/I0</td>
</tr>
<tr>
<td>12.721</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R6C49[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_1/n380_s0/F</td>
</tr>
<tr>
<td>12.721</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.245</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C49[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_4_s0/CLK</td>
</tr>
<tr>
<td>6.184</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C49[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.372, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.372, 51.598%; route: 5.610, 45.428%; tC2Q: 0.367, 2.973%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.363, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.532</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.677</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.145</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.356</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C30[0][B]</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/CLK</td>
</tr>
<tr>
<td>0.724</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R5C30[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
</tr>
<tr>
<td>1.531</td>
<td>0.808</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s6/I3</td>
</tr>
<tr>
<td>2.032</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R9C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.562</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s2/I3</td>
</tr>
<tr>
<td>3.067</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C28[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s2/F</td>
</tr>
<tr>
<td>3.736</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s0/I2</td>
</tr>
<tr>
<td>3.988</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C28[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>6.358</td>
<td>2.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n175_s21/I0</td>
</tr>
<tr>
<td>6.636</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R11C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n175_s21/F</td>
</tr>
<tr>
<td>6.829</td>
<td>0.193</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C26[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n174_s17/I0</td>
</tr>
<tr>
<td>7.334</td>
<td>0.505</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R11C26[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n174_s17/F</td>
</tr>
<tr>
<td>7.679</td>
<td>0.344</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C25[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n173_s11/I1</td>
</tr>
<tr>
<td>8.156</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R12C25[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n173_s11/F</td>
</tr>
<tr>
<td>8.298</td>
<td>0.142</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R12C25[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n324_s/I1</td>
</tr>
<tr>
<td>8.771</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n324_s/COUT</td>
</tr>
<tr>
<td>8.771</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R12C25[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n323_s/CIN</td>
</tr>
<tr>
<td>8.819</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C25[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n323_s/COUT</td>
</tr>
<tr>
<td>8.819</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R12C25[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n322_s/CIN</td>
</tr>
<tr>
<td>9.103</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n322_s/SUM</td>
</tr>
<tr>
<td>9.518</td>
<td>0.415</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C25[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n322_s0/I0</td>
</tr>
<tr>
<td>10.052</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n322_s0/COUT</td>
</tr>
<tr>
<td>10.052</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C26[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n321_s0/CIN</td>
</tr>
<tr>
<td>10.286</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R11C26[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n321_s0/SUM</td>
</tr>
<tr>
<td>10.807</td>
<td>0.521</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C22[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n377_s5/I0</td>
</tr>
<tr>
<td>11.303</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C22[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n377_s5/F</td>
</tr>
<tr>
<td>11.306</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C22[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n377_s3/I0</td>
</tr>
<tr>
<td>11.749</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C22[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n377_s3/F</td>
</tr>
<tr>
<td>11.753</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C22[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n377_s1/I0</td>
</tr>
<tr>
<td>12.230</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C22[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n377_s1/F</td>
</tr>
<tr>
<td>12.234</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n377_s0/I0</td>
</tr>
<tr>
<td>12.677</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C22[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n377_s0/F</td>
</tr>
<tr>
<td>12.677</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C22[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.206</td>
<td>0.324</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_7_s0/CLK</td>
</tr>
<tr>
<td>6.145</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.032</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.356, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.951, 48.300%; route: 6.002, 48.719%; tC2Q: 0.367, 2.980%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.324, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.524</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.715</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.191</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.381</td>
<td>0.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/CLK</td>
</tr>
<tr>
<td>0.748</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R24C47[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_0_s0/Q</td>
</tr>
<tr>
<td>2.392</td>
<td>1.644</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n407_s3/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C45[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>3.065</td>
<td>0.168</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n404_s3/I3</td>
</tr>
<tr>
<td>3.317</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R11C44[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n404_s3/F</td>
</tr>
<tr>
<td>3.845</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s4/I3</td>
</tr>
<tr>
<td>4.351</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R9C44[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>4.508</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s3/I0</td>
</tr>
<tr>
<td>4.951</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C43[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>5.104</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>5.547</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>6.215</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s14/I2</td>
</tr>
<tr>
<td>6.711</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s14/F</td>
</tr>
<tr>
<td>6.875</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n146_s10/I3</td>
</tr>
<tr>
<td>7.381</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>8.092</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C45[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>8.371</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R7C45[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>8.493</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C45[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n245_s/I1</td>
</tr>
<tr>
<td>8.966</td>
<td>0.473</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C45[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n245_s/COUT</td>
</tr>
<tr>
<td>8.966</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C45[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s/CIN</td>
</tr>
<tr>
<td>9.250</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C45[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s/SUM</td>
</tr>
<tr>
<td>9.651</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C46[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n326_s0/I0</td>
</tr>
<tr>
<td>10.185</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C46[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n326_s0/COUT</td>
</tr>
<tr>
<td>10.185</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R7C46[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n325_s0/CIN</td>
</tr>
<tr>
<td>10.233</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C46[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n325_s0/COUT</td>
</tr>
<tr>
<td>10.233</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C47[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n324_s0/CIN</td>
</tr>
<tr>
<td>10.467</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R7C47[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n324_s0/SUM</td>
</tr>
<tr>
<td>11.273</td>
<td>0.806</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C44[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n381_s3/I3</td>
</tr>
<tr>
<td>11.769</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C44[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n381_s3/F</td>
</tr>
<tr>
<td>11.773</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C44[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n381_s1/I0</td>
</tr>
<tr>
<td>12.268</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C44[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n381_s1/F</td>
</tr>
<tr>
<td>12.272</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/n381_s0/I0</td>
</tr>
<tr>
<td>12.715</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R7C44[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_2/n381_s0/F</td>
</tr>
<tr>
<td>12.715</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C44[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.252</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_3_s0/CLK</td>
</tr>
<tr>
<td>6.191</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.011</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.381, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.434, 52.170%; route: 5.532, 44.853%; tC2Q: 0.367, 2.977%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.410</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.545</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.135</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.356</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C30[0][B]</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/CLK</td>
</tr>
<tr>
<td>0.724</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R5C30[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
</tr>
<tr>
<td>1.531</td>
<td>0.808</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s6/I3</td>
</tr>
<tr>
<td>2.032</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R9C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.562</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s2/I3</td>
</tr>
<tr>
<td>3.067</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C28[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s2/F</td>
</tr>
<tr>
<td>3.736</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s0/I2</td>
</tr>
<tr>
<td>3.988</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C28[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>5.873</td>
<td>1.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C27[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n175_s16/I0</td>
</tr>
<tr>
<td>6.368</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R12C27[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n175_s16/F</td>
</tr>
<tr>
<td>6.788</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C26[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n174_s16/I3</td>
</tr>
<tr>
<td>7.294</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C26[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n174_s16/F</td>
</tr>
<tr>
<td>7.451</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C26[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n174_s15/I0</td>
</tr>
<tr>
<td>7.951</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R12C26[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n174_s15/F</td>
</tr>
<tr>
<td>8.108</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R12C25[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n325_s/I1</td>
</tr>
<tr>
<td>8.581</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C25[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n325_s/COUT</td>
</tr>
<tr>
<td>8.581</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R12C25[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n324_s/CIN</td>
</tr>
<tr>
<td>8.866</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n324_s/SUM</td>
</tr>
<tr>
<td>9.281</td>
<td>0.415</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n324_s0/I0</td>
</tr>
<tr>
<td>9.983</td>
<td>0.702</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n324_s0/SUM</td>
</tr>
<tr>
<td>10.307</td>
<td>0.324</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C23[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n378_s5/I0</td>
</tr>
<tr>
<td>10.812</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R11C23[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n378_s5/F</td>
</tr>
<tr>
<td>11.156</td>
<td>0.344</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n380_s3/I1</td>
</tr>
<tr>
<td>11.599</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C22[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n380_s3/F</td>
</tr>
<tr>
<td>11.603</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n380_s1/I0</td>
</tr>
<tr>
<td>12.098</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C22[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n380_s1/F</td>
</tr>
<tr>
<td>12.102</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n380_s0/I0</td>
</tr>
<tr>
<td>12.545</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C22[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n380_s0/F</td>
</tr>
<tr>
<td>12.545</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.196</td>
<td>0.314</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_4_s0/CLK</td>
</tr>
<tr>
<td>6.135</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C22[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.043</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.356, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.104, 50.084%; route: 5.717, 46.904%; tC2Q: 0.367, 3.013%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.314, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.390</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.581</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.191</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.347</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/CLK</td>
</tr>
<tr>
<td>0.714</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R27C33[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
</tr>
<tr>
<td>2.359</td>
<td>1.645</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n407_s3/I3</td>
</tr>
<tr>
<td>2.611</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R29C28[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>2.622</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s4/I2</td>
</tr>
<tr>
<td>3.020</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C28[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s4/F</td>
</tr>
<tr>
<td>3.178</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s2/I2</td>
</tr>
<tr>
<td>3.673</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>3.680</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>3.932</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>4.586</td>
<td>0.654</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>5.029</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R27C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.547</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s13/I3</td>
</tr>
<tr>
<td>6.082</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s13/F</td>
</tr>
<tr>
<td>6.096</td>
<td>0.014</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s10/I2</td>
</tr>
<tr>
<td>6.539</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s10/F</td>
</tr>
<tr>
<td>6.882</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n176_s13/I0</td>
</tr>
<tr>
<td>7.360</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R26C24[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n176_s13/F</td>
</tr>
<tr>
<td>8.174</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n223_s/I1</td>
</tr>
<tr>
<td>8.647</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n223_s/COUT</td>
</tr>
<tr>
<td>8.647</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n289_s/CIN</td>
</tr>
<tr>
<td>8.695</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n289_s/COUT</td>
</tr>
<tr>
<td>8.695</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s/CIN</td>
</tr>
<tr>
<td>8.929</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s/SUM</td>
</tr>
<tr>
<td>9.733</td>
<td>0.804</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R27C25[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s0/I0</td>
</tr>
<tr>
<td>10.267</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R27C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s0/COUT</td>
</tr>
<tr>
<td>10.267</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R27C26[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n287_s0/CIN</td>
</tr>
<tr>
<td>10.501</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R27C26[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n287_s0/SUM</td>
</tr>
<tr>
<td>11.005</td>
<td>0.504</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C25[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s6/I3</td>
</tr>
<tr>
<td>11.404</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C25[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n378_s6/F</td>
</tr>
<tr>
<td>11.564</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s4/I2</td>
</tr>
<tr>
<td>11.816</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C24[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n378_s4/F</td>
</tr>
<tr>
<td>11.820</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s1/I1</td>
</tr>
<tr>
<td>12.072</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C24[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n378_s1/F</td>
</tr>
<tr>
<td>12.076</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n378_s0/I0</td>
</tr>
<tr>
<td>12.581</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R25C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n378_s0/F</td>
</tr>
<tr>
<td>12.581</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.252</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_6_s0/CLK</td>
</tr>
<tr>
<td>6.191</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.023</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>17</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.197, 50.652%; route: 5.670, 46.346%; tC2Q: 0.367, 3.001%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.372</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.537</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.345</td>
<td>0.345</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C30[0][B]</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_1_s0/CLK</td>
</tr>
<tr>
<td>0.698</td>
<td>0.353</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R8C30[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_enc/out_axis_tdata_1_s0/Q</td>
</tr>
<tr>
<td>2.132</td>
<td>1.434</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C23[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n407_s3/I3</td>
</tr>
<tr>
<td>2.627</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R15C23[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n407_s3/F</td>
</tr>
<tr>
<td>2.792</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C24[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s8/I1</td>
</tr>
<tr>
<td>3.190</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R15C24[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n88_s8/F</td>
</tr>
<tr>
<td>3.354</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C25[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s4/I3</td>
</tr>
<tr>
<td>3.832</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R15C25[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n88_s4/F</td>
</tr>
<tr>
<td>3.993</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C24[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s3/I0</td>
</tr>
<tr>
<td>4.493</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R15C24[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n88_s3/F</td>
</tr>
<tr>
<td>4.650</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C25[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n88_s0/I3</td>
</tr>
<tr>
<td>5.146</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>29</td>
<td>R15C25[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n88_s0/F</td>
</tr>
<tr>
<td>5.692</td>
<td>0.546</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C23[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n146_s13/I3</td>
</tr>
<tr>
<td>6.197</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R15C23[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n146_s13/F</td>
</tr>
<tr>
<td>6.540</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C24[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n146_s10/I2</td>
</tr>
<tr>
<td>6.792</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R16C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n146_s10/F</td>
</tr>
<tr>
<td>7.164</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C27[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n176_s13/I0</td>
</tr>
<tr>
<td>7.563</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R16C27[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n176_s13/F</td>
</tr>
<tr>
<td>7.701</td>
<td>0.138</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R16C27[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n245_s/I1</td>
</tr>
<tr>
<td>8.174</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R16C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n245_s/COUT</td>
</tr>
<tr>
<td>8.174</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R16C27[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n326_s/CIN</td>
</tr>
<tr>
<td>8.222</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R16C27[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n326_s/COUT</td>
</tr>
<tr>
<td>8.222</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R16C27[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n325_s/CIN</td>
</tr>
<tr>
<td>8.270</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R16C27[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n325_s/COUT</td>
</tr>
<tr>
<td>8.270</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R16C27[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n324_s/CIN</td>
</tr>
<tr>
<td>8.554</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R16C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n324_s/SUM</td>
</tr>
<tr>
<td>9.021</td>
<td>0.467</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R17C27[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n324_s0/I0</td>
</tr>
<tr>
<td>9.723</td>
<td>0.702</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R17C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n324_s0/SUM</td>
</tr>
<tr>
<td>10.065</td>
<td>0.342</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C26[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n378_s5/I0</td>
</tr>
<tr>
<td>10.565</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R16C26[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n378_s5/F</td>
</tr>
<tr>
<td>11.042</td>
<td>0.476</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n380_s3/I1</td>
</tr>
<tr>
<td>11.547</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C28[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n380_s3/F</td>
</tr>
<tr>
<td>11.550</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n380_s1/I0</td>
</tr>
<tr>
<td>12.028</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n380_s1/F</td>
</tr>
<tr>
<td>12.032</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/n380_s0/I0</td>
</tr>
<tr>
<td>12.537</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C28[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_2/n380_s0/F</td>
</tr>
<tr>
<td>12.537</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_2/cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.226</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_4_s0/CLK</td>
</tr>
<tr>
<td>6.164</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C28[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.345, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.067, 57.963%; route: 4.772, 39.144%; tC2Q: 0.353, 2.894%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.343, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.323</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.129</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.356</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C30[0][B]</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/CLK</td>
</tr>
<tr>
<td>0.724</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R5C30[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
</tr>
<tr>
<td>1.531</td>
<td>0.808</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s6/I3</td>
</tr>
<tr>
<td>2.032</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R9C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.562</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s2/I3</td>
</tr>
<tr>
<td>3.067</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C28[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s2/F</td>
</tr>
<tr>
<td>3.736</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s0/I2</td>
</tr>
<tr>
<td>3.988</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C28[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>6.358</td>
<td>2.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n175_s21/I0</td>
</tr>
<tr>
<td>6.636</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R11C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n175_s21/F</td>
</tr>
<tr>
<td>6.829</td>
<td>0.193</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C26[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n174_s17/I0</td>
</tr>
<tr>
<td>7.334</td>
<td>0.505</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R11C26[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n174_s17/F</td>
</tr>
<tr>
<td>7.679</td>
<td>0.344</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C25[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n173_s11/I1</td>
</tr>
<tr>
<td>8.156</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R12C25[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n173_s11/F</td>
</tr>
<tr>
<td>8.298</td>
<td>0.142</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R12C25[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n324_s/I1</td>
</tr>
<tr>
<td>8.771</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n324_s/COUT</td>
</tr>
<tr>
<td>8.771</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R12C25[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n323_s/CIN</td>
</tr>
<tr>
<td>8.819</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C25[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n323_s/COUT</td>
</tr>
<tr>
<td>8.819</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R12C25[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n322_s/CIN</td>
</tr>
<tr>
<td>9.103</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n322_s/SUM</td>
</tr>
<tr>
<td>9.518</td>
<td>0.415</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C25[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n322_s0/I0</td>
</tr>
<tr>
<td>10.052</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n322_s0/COUT</td>
</tr>
<tr>
<td>10.052</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C26[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n321_s0/CIN</td>
</tr>
<tr>
<td>10.286</td>
<td>0.234</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R11C26[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n321_s0/SUM</td>
</tr>
<tr>
<td>10.992</td>
<td>0.706</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C22[2][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n378_s3/I3</td>
</tr>
<tr>
<td>11.497</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C22[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n378_s3/F</td>
</tr>
<tr>
<td>11.501</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C22[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n378_s1/I0</td>
</tr>
<tr>
<td>11.944</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C22[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n378_s1/F</td>
</tr>
<tr>
<td>11.947</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n378_s0/I0</td>
</tr>
<tr>
<td>12.452</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C22[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n378_s0/F</td>
</tr>
<tr>
<td>12.452</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C22[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.190</td>
<td>0.308</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_6_s0/CLK</td>
</tr>
<tr>
<td>6.129</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.048</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.356, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.545, 45.843%; route: 6.184, 51.121%; tC2Q: 0.367, 3.036%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.308, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.293</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.437</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.144</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.372</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/CLK</td>
</tr>
<tr>
<td>0.739</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R24C44[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/Q</td>
</tr>
<tr>
<td>1.782</td>
<td>1.043</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C50[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s6/I2</td>
</tr>
<tr>
<td>2.225</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R22C50[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.232</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C50[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s5/I2</td>
</tr>
<tr>
<td>2.728</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R22C50[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s5/F</td>
</tr>
<tr>
<td>2.917</td>
<td>0.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C50[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s3/I3</td>
</tr>
<tr>
<td>3.360</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C50[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s3/F</td>
</tr>
<tr>
<td>3.494</td>
<td>0.134</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C50[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s0/I3</td>
</tr>
<tr>
<td>3.893</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>32</td>
<td>R21C50[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>5.480</td>
<td>1.588</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C52[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n175_s16/I3</td>
</tr>
<tr>
<td>5.976</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R20C52[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n175_s16/F</td>
</tr>
<tr>
<td>6.632</td>
<td>0.656</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C52[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n260_s2/I1</td>
</tr>
<tr>
<td>7.138</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C52[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n260_s2/F</td>
</tr>
<tr>
<td>7.512</td>
<td>0.374</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C52[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n174_s15/I1</td>
</tr>
<tr>
<td>7.955</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R14C52[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n174_s15/F</td>
</tr>
<tr>
<td>8.116</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R14C51[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n325_s/I1</td>
</tr>
<tr>
<td>8.588</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R14C51[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n325_s/COUT</td>
</tr>
<tr>
<td>8.588</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R14C51[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n324_s/CIN</td>
</tr>
<tr>
<td>8.873</td>
<td>0.284</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R14C51[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n324_s/SUM</td>
</tr>
<tr>
<td>9.340</td>
<td>0.467</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R15C51[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n324_s0/I0</td>
</tr>
<tr>
<td>10.042</td>
<td>0.702</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R15C51[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n324_s0/SUM</td>
</tr>
<tr>
<td>10.199</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C51[3][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n378_s5/I0</td>
</tr>
<tr>
<td>10.676</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R14C51[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n378_s5/F</td>
</tr>
<tr>
<td>11.022</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n378_s3/I2</td>
</tr>
<tr>
<td>11.527</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C52[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n378_s3/F</td>
</tr>
<tr>
<td>11.531</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[3][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n378_s1/I0</td>
</tr>
<tr>
<td>12.031</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C52[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n378_s1/F</td>
</tr>
<tr>
<td>12.185</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n378_s0/I0</td>
</tr>
<tr>
<td>12.437</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C51[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n378_s0/F</td>
</tr>
<tr>
<td>12.437</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_0/cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.205</td>
<td>0.323</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_6_s0/CLK</td>
</tr>
<tr>
<td>6.144</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C51[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.049</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.372, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.418, 53.193%; route: 5.280, 43.764%; tC2Q: 0.367, 3.044%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.323, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.269</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.175</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.347</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td>svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/CLK</td>
</tr>
<tr>
<td>0.714</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R27C33[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/out_axis_tdata_9_s0/Q</td>
</tr>
<tr>
<td>2.359</td>
<td>1.645</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n407_s3/I3</td>
</tr>
<tr>
<td>2.611</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R29C28[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n407_s3/F</td>
</tr>
<tr>
<td>2.622</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s4/I2</td>
</tr>
<tr>
<td>3.020</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C28[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s4/F</td>
</tr>
<tr>
<td>3.178</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s2/I2</td>
</tr>
<tr>
<td>3.673</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R29C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s2/F</td>
</tr>
<tr>
<td>3.680</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s3/I3</td>
</tr>
<tr>
<td>3.932</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s3/F</td>
</tr>
<tr>
<td>4.586</td>
<td>0.654</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n88_s0/I3</td>
</tr>
<tr>
<td>5.029</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R27C27[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n88_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.547</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s13/I3</td>
</tr>
<tr>
<td>6.082</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s13/F</td>
</tr>
<tr>
<td>6.096</td>
<td>0.014</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C26[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n146_s10/I2</td>
</tr>
<tr>
<td>6.539</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R25C26[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n146_s10/F</td>
</tr>
<tr>
<td>6.882</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[3][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n176_s13/I0</td>
</tr>
<tr>
<td>7.360</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R26C24[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n176_s13/F</td>
</tr>
<tr>
<td>8.174</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n223_s/I1</td>
</tr>
<tr>
<td>8.647</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n223_s/COUT</td>
</tr>
<tr>
<td>8.647</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n289_s/CIN</td>
</tr>
<tr>
<td>8.695</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n289_s/COUT</td>
</tr>
<tr>
<td>8.695</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R29C24[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s/CIN</td>
</tr>
<tr>
<td>8.929</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s/SUM</td>
</tr>
<tr>
<td>9.733</td>
<td>0.804</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R27C25[2][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n288_s0/I0</td>
</tr>
<tr>
<td>10.435</td>
<td>0.702</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R27C25[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n288_s0/SUM</td>
</tr>
<tr>
<td>11.090</td>
<td>0.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n382_s4/I2</td>
</tr>
<tr>
<td>11.596</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C23[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n382_s4/F</td>
</tr>
<tr>
<td>11.599</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n382_s1/I1</td>
</tr>
<tr>
<td>11.998</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C23[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n382_s1/F</td>
</tr>
<tr>
<td>12.001</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/n382_s0/I0</td>
</tr>
<tr>
<td>12.444</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C23[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/svo_tmds_1/n382_s0/F</td>
</tr>
<tr>
<td>12.444</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.236</td>
<td>0.354</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_2_s0/CLK</td>
</tr>
<tr>
<td>6.175</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C23[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.007</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.070, 50.174%; route: 5.660, 46.791%; tC2Q: 0.367, 3.035%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.354, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.257</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.392</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.135</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.356</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C30[0][B]</td>
<td>svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/CLK</td>
</tr>
<tr>
<td>0.724</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R5C30[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_enc/out_axis_tdata_17_s0/Q</td>
</tr>
<tr>
<td>1.531</td>
<td>0.808</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[3][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s6/I3</td>
</tr>
<tr>
<td>2.032</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R9C28[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.562</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C28[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s2/I3</td>
</tr>
<tr>
<td>3.067</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R11C28[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s2/F</td>
</tr>
<tr>
<td>3.736</td>
<td>0.668</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C28[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n88_s0/I2</td>
</tr>
<tr>
<td>3.988</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>30</td>
<td>R9C28[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>6.096</td>
<td>2.108</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C28[2][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n146_s13/I0</td>
</tr>
<tr>
<td>6.539</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R12C28[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n146_s13/F</td>
</tr>
<tr>
<td>6.883</td>
<td>0.344</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C26[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n146_s10/I3</td>
</tr>
<tr>
<td>7.326</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R12C26[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n146_s10/F</td>
</tr>
<tr>
<td>7.830</td>
<td>0.504</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C25[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n289_s/I1</td>
</tr>
<tr>
<td>8.303</td>
<td>0.473</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C25[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n289_s/COUT</td>
</tr>
<tr>
<td>8.303</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C25[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n288_s/CIN</td>
</tr>
<tr>
<td>8.537</td>
<td>0.234</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C25[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n288_s/SUM</td>
</tr>
<tr>
<td>8.873</td>
<td>0.336</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R14C25[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n288_s0/I0</td>
</tr>
<tr>
<td>9.575</td>
<td>0.702</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R14C25[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n288_s0/SUM</td>
</tr>
<tr>
<td>10.100</td>
<td>0.526</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C23[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n378_s6/I1</td>
</tr>
<tr>
<td>10.606</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R12C23[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n378_s6/F</td>
</tr>
<tr>
<td>10.951</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n379_s4/I1</td>
</tr>
<tr>
<td>11.394</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R14C22[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n379_s4/F</td>
</tr>
<tr>
<td>11.548</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[3][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n379_s1/I1</td>
</tr>
<tr>
<td>11.946</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C22[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n379_s1/F</td>
</tr>
<tr>
<td>11.950</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/n379_s0/I0</td>
</tr>
<tr>
<td>12.392</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C22[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_1/svo_tmds_0/n379_s0/F</td>
</tr>
<tr>
<td>12.392</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.196</td>
<td>0.314</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_5_s0/CLK</td>
</tr>
<tr>
<td>6.135</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C22[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.043</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>13</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.356, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.341, 44.377%; route: 6.328, 52.572%; tC2Q: 0.367, 3.051%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.314, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-6.247</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.404</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.157</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.372</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C44[0][A]</td>
<td>svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/CLK</td>
</tr>
<tr>
<td>0.739</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R24C44[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_axis_tdata_20_s0/Q</td>
</tr>
<tr>
<td>1.782</td>
<td>1.043</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C50[1][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s6/I2</td>
</tr>
<tr>
<td>2.225</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R22C50[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s6/F</td>
</tr>
<tr>
<td>2.232</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C50[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s5/I2</td>
</tr>
<tr>
<td>2.728</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R22C50[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s5/F</td>
</tr>
<tr>
<td>2.917</td>
<td>0.190</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C50[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s3/I3</td>
</tr>
<tr>
<td>3.360</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C50[2][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s3/F</td>
</tr>
<tr>
<td>3.494</td>
<td>0.134</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C50[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n88_s0/I3</td>
</tr>
<tr>
<td>3.893</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>32</td>
<td>R21C50[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n88_s0/F</td>
</tr>
<tr>
<td>5.480</td>
<td>1.588</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C52[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n175_s16/I3</td>
</tr>
<tr>
<td>5.976</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R20C52[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n175_s16/F</td>
</tr>
<tr>
<td>6.632</td>
<td>0.656</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C52[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n260_s2/I1</td>
</tr>
<tr>
<td>7.138</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C52[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n260_s2/F</td>
</tr>
<tr>
<td>7.512</td>
<td>0.374</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C52[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n174_s15/I1</td>
</tr>
<tr>
<td>7.955</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R14C52[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n174_s15/F</td>
</tr>
<tr>
<td>8.480</td>
<td>0.526</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C51[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n180_s0/I0</td>
</tr>
<tr>
<td>9.014</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C51[0][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n180_s0/COUT</td>
</tr>
<tr>
<td>9.014</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C51[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n181_s0/CIN</td>
</tr>
<tr>
<td>9.062</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C51[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n181_s0/COUT</td>
</tr>
<tr>
<td>9.482</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C51[3][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n183_s0/I2</td>
</tr>
<tr>
<td>9.960</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>10</td>
<td>R16C51[3][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n183_s0/F</td>
</tr>
<tr>
<td>10.822</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C51[2][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n359_s1/I2</td>
</tr>
<tr>
<td>11.074</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R20C51[2][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n359_s1/F</td>
</tr>
<tr>
<td>11.927</td>
<td>0.853</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C51[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/n359_s0/I2</td>
</tr>
<tr>
<td>12.404</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R16C51[3][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_2/svo_tmds_0/n359_s0/F</td>
</tr>
<tr>
<td>12.404</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C51[3][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_0/cnt_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.218</td>
<td>0.336</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C51[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_0_s0/CLK</td>
</tr>
<tr>
<td>6.157</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R16C51[3][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_0/cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.036</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>13</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.372, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.012, 41.658%; route: 6.653, 55.291%; tC2Q: 0.367, 3.052%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.336, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.223</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.470</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.246</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C22[1][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_9_s0/CLK</td>
</tr>
<tr>
<td>0.357</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R23C22[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/q_out_9_s0/Q</td>
</tr>
<tr>
<td>0.470</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C22</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.186</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C22</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8/CLK</td>
</tr>
<tr>
<td>0.246</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C22</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.113, 39.496%; tC2Q: 0.173, 60.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.186, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.224</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.468</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.244</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.182</td>
<td>0.182</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C50[2][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_2_s0/CLK</td>
</tr>
<tr>
<td>0.355</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R6C50[2][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/q_out_2_s0/Q</td>
</tr>
<tr>
<td>0.468</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C50</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C50</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.244</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C50</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.182, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.113, 39.496%; tC2Q: 0.173, 60.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.224</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.475</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.251</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.189</td>
<td>0.189</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C23[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_3_s0/CLK</td>
</tr>
<tr>
<td>0.362</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R23C23[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/q_out_3_s0/Q</td>
</tr>
<tr>
<td>0.475</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.191</td>
<td>0.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.251</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C23</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.189, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.113, 39.496%; tC2Q: 0.173, 60.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.191, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.228</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.479</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.251</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.193</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C23[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_1_s0/CLK</td>
</tr>
<tr>
<td>0.366</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R21C23[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/q_out_1_s0/Q</td>
</tr>
<tr>
<td>0.479</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.191</td>
<td>0.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.251</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C23</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.002</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.193, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.113, 39.496%; tC2Q: 0.173, 60.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.191, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.230</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.458</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.228</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_1/q_out_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.173</td>
<td>0.173</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C23[1][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/q_out_3_s0/CLK</td>
</tr>
<tr>
<td>0.346</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R27C23[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/q_out_3_s0/Q</td>
</tr>
<tr>
<td>0.458</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C22</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s4/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.168</td>
<td>0.168</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C22</td>
<td>svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.228</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C22</td>
<td>svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.005</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.173, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.113, 39.496%; tC2Q: 0.173, 60.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.168, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.230</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.479</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.248</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.193</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C23[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_4_s0/CLK</td>
</tr>
<tr>
<td>0.366</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R21C23[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/q_out_4_s0/Q</td>
</tr>
<tr>
<td>0.479</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C22</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.188</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C22</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6/CLK</td>
</tr>
<tr>
<td>0.248</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C22</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.005</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.193, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.113, 39.496%; tC2Q: 0.173, 60.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.188, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.230</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.475</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.244</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.189</td>
<td>0.189</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C51[1][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_3_s0/CLK</td>
</tr>
<tr>
<td>0.362</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R5C51[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/q_out_3_s0/Q</td>
</tr>
<tr>
<td>0.475</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C50</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C50</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.244</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C50</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.005</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.189, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.113, 39.496%; tC2Q: 0.173, 60.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.230</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.475</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.244</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.189</td>
<td>0.189</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C51[0][B]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_0_s0/CLK</td>
</tr>
<tr>
<td>0.362</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R5C51[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/q_out_0_s0/Q</td>
</tr>
<tr>
<td>0.475</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C50</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C50</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.244</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C50</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.005</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.189, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.113, 39.496%; tC2Q: 0.173, 60.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.235</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.495</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.260</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.202</td>
<td>0.202</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C45[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s2/CLK</td>
</tr>
<tr>
<td>0.375</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>55</td>
<td>R3C45[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s2/Q</td>
</tr>
<tr>
<td>0.495</td>
<td>0.120</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s4/AD[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.200</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.260</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C45</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.002</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.202, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.120, 40.984%; tC2Q: 0.173, 59.016%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.200, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.241</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.464</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.223</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_tmds_2/q_out_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.172</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C24[1][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/q_out_3_s0/CLK</td>
</tr>
<tr>
<td>0.345</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R17C24[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_2/q_out_3_s0/Q</td>
</tr>
<tr>
<td>0.464</td>
<td>0.119</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.163</td>
<td>0.163</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22</td>
<td>svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.223</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C22</td>
<td>svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.172, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.119, 40.741%; tC2Q: 0.173, 59.259%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.163, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.242</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.497</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.256</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_enc/ctrl_fifo_rdaddr_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_enc/out_fifo_out_fifo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.194</td>
<td>0.194</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C47[1][A]</td>
<td>svo_hdmi_inst_2/svo_enc/ctrl_fifo_rdaddr_1_s0/CLK</td>
</tr>
<tr>
<td>0.367</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>22</td>
<td>R25C47[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/ctrl_fifo_rdaddr_1_s0/Q</td>
</tr>
<tr>
<td>0.497</td>
<td>0.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C47</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_enc/out_fifo_out_fifo_0_0_s/WAD[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.196</td>
<td>0.196</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C47</td>
<td>svo_hdmi_inst_2/svo_enc/out_fifo_out_fifo_0_0_s/CLK</td>
</tr>
<tr>
<td>0.256</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R24C47</td>
<td>svo_hdmi_inst_2/svo_enc/out_fifo_out_fifo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.194, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.131, 43.083%; tC2Q: 0.173, 56.917%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.196, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.564</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.246</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.182</td>
<td>0.182</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C22[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_8_s0/CLK</td>
</tr>
<tr>
<td>0.355</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R24C22[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/q_out_8_s0/Q</td>
</tr>
<tr>
<td>0.564</td>
<td>0.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C22</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.186</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C22</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8/CLK</td>
</tr>
<tr>
<td>0.246</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C22</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s8</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.004</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.182, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.209, 54.717%; tC2Q: 0.173, 45.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.186, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.566</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.248</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C22[2][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_6_s0/CLK</td>
</tr>
<tr>
<td>0.357</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R23C22[2][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/q_out_6_s0/Q</td>
</tr>
<tr>
<td>0.566</td>
<td>0.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C22</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.188</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C22</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6/CLK</td>
</tr>
<tr>
<td>0.248</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C22</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s6</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.004</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.209, 54.717%; tC2Q: 0.173, 45.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.188, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.322</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.571</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.249</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s8</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.189</td>
<td>0.189</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C51[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_1/q_out_8_s0/CLK</td>
</tr>
<tr>
<td>0.362</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R5C51[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/q_out_8_s0/Q</td>
</tr>
<tr>
<td>0.571</td>
<td>0.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C49</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s8/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.189</td>
<td>0.189</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C49</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s8/CLK</td>
</tr>
<tr>
<td>0.249</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C49</td>
<td>svo_hdmi_inst_2/svo_tmds_1/dout_buf2_0_s8</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.189, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.209, 54.717%; tC2Q: 0.173, 45.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.189, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.322</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.554</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.233</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.173</td>
<td>0.173</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C25[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_1_s0/CLK</td>
</tr>
<tr>
<td>0.346</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R9C25[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/q_out_1_s0/Q</td>
</tr>
<tr>
<td>0.554</td>
<td>0.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C23</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s4/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.173</td>
<td>0.173</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C23</td>
<td>svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.233</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C23</td>
<td>svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.173, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.209, 54.717%; tC2Q: 0.173, 45.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.173, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.328</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.264</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/svo_tmds_2/q_out_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s8</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.191</td>
<td>0.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C43[0][A]</td>
<td>svo_hdmi_inst_2/svo_tmds_2/q_out_8_s0/CLK</td>
</tr>
<tr>
<td>0.364</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C43[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/q_out_8_s0/Q</td>
</tr>
<tr>
<td>0.592</td>
<td>0.228</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C46</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s8/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.204</td>
<td>0.204</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C46</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s8/CLK</td>
</tr>
<tr>
<td>0.264</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C46</td>
<td>svo_hdmi_inst_2/svo_tmds_2/dout_buf2_0_s8</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.191, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.204, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.329</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.585</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.256</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_tmds_1/q_out_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s6</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C26[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_1/q_out_5_s0/CLK</td>
</tr>
<tr>
<td>0.357</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R5C26[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_1/q_out_5_s0/Q</td>
</tr>
<tr>
<td>0.585</td>
<td>0.228</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C24</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s6/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.196</td>
<td>0.196</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C24</td>
<td>svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s6/CLK</td>
</tr>
<tr>
<td>0.256</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C24</td>
<td>svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s6</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.012</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.196, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.331</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.565</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.234</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_1/q_out_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s6</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[3][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_1/q_out_7_s0/CLK</td>
</tr>
<tr>
<td>0.356</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R26C24[3][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/q_out_7_s0/Q</td>
</tr>
<tr>
<td>0.565</td>
<td>0.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C22</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s6/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.174</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C22</td>
<td>svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s6/CLK</td>
</tr>
<tr>
<td>0.234</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C22</td>
<td>svo_hdmi_inst_0/svo_tmds_1/dout_buf2_0_s6</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.209, 54.717%; tC2Q: 0.173, 45.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.174, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.331</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.554</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.223</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_tmds_2/q_out_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.172</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C24[0][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_2/q_out_2_s0/CLK</td>
</tr>
<tr>
<td>0.345</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R17C24[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_2/q_out_2_s0/Q</td>
</tr>
<tr>
<td>0.554</td>
<td>0.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.163</td>
<td>0.163</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22</td>
<td>svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.223</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C22</td>
<td>svo_hdmi_inst_1/svo_tmds_2/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.172, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.209, 54.717%; tC2Q: 0.173, 45.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.163, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.334</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.585</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.251</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_tmds_1/q_out_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C26[0][A]</td>
<td>svo_hdmi_inst_1/svo_tmds_1/q_out_3_s0/CLK</td>
</tr>
<tr>
<td>0.357</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R5C26[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_1/q_out_3_s0/Q</td>
</tr>
<tr>
<td>0.585</td>
<td>0.228</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C25</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s4/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.191</td>
<td>0.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C25</td>
<td>svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.251</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C25</td>
<td>svo_hdmi_inst_1/svo_tmds_1/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.007</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.191, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.334</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.585</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.251</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C22[0][B]</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_2_s0/CLK</td>
</tr>
<tr>
<td>0.357</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R23C22[0][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/q_out_2_s0/Q</td>
</tr>
<tr>
<td>0.585</td>
<td>0.228</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.191</td>
<td>0.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.251</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C23</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.007</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.191, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.334</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.585</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.251</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C22[0][A]</td>
<td>svo_hdmi_inst_0/svo_tmds_0/q_out_0_s0/CLK</td>
</tr>
<tr>
<td>0.357</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R23C22[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/q_out_0_s0/Q</td>
</tr>
<tr>
<td>0.585</td>
<td>0.228</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.191</td>
<td>0.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4/CLK</td>
</tr>
<tr>
<td>0.251</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C23</td>
<td>svo_hdmi_inst_0/svo_tmds_0/dout_buf2_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.007</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.191, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.335</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.556</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.221</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/ctrl_fifo_rdaddr_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.155</td>
<td>0.155</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C31[2][A]</td>
<td>svo_hdmi_inst_0/svo_enc/ctrl_fifo_rdaddr_1_s0/CLK</td>
</tr>
<tr>
<td>0.328</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>22</td>
<td>R31C31[2][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/ctrl_fifo_rdaddr_1_s0/Q</td>
</tr>
<tr>
<td>0.556</td>
<td>0.228</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s/WAD[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.161</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31</td>
<td>svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s/CLK</td>
</tr>
<tr>
<td>0.221</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C31</td>
<td>svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.006</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.155, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.161, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.336</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.557</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.221</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_0/svo_enc/ctrl_fifo_rdaddr_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.155</td>
<td>0.155</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C31[0][A]</td>
<td>svo_hdmi_inst_0/svo_enc/ctrl_fifo_rdaddr_0_s2/CLK</td>
</tr>
<tr>
<td>0.328</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>19</td>
<td>R31C31[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/ctrl_fifo_rdaddr_0_s2/Q</td>
</tr>
<tr>
<td>0.557</td>
<td>0.229</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s/WAD[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.161</td>
<td>0.161</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31</td>
<td>svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s/CLK</td>
</tr>
<tr>
<td>0.221</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C31</td>
<td>svo_hdmi_inst_0/svo_enc/out_fifo_out_fifo_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.006</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.155, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.229, 57.015%; tC2Q: 0.173, 42.985%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.161, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.336</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.574</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.238</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s8</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.173</td>
<td>0.173</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C27[1][B]</td>
<td>svo_hdmi_inst_1/svo_tmds_0/q_out_8_s0/CLK</td>
</tr>
<tr>
<td>0.346</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R9C27[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/q_out_8_s0/Q</td>
</tr>
<tr>
<td>0.574</td>
<td>0.228</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C24</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s8/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.178</td>
<td>0.178</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C24</td>
<td>svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s8/CLK</td>
</tr>
<tr>
<td>0.238</td>
<td>0.060</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C24</td>
<td>svo_hdmi_inst_1/svo_tmds_0/dout_buf2_0_s8</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.005</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.173, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.178, 100.000%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.618</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT66[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT66[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_2/tmds_serdes[0]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT66[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.618</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT68[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT68[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_2/tmds_serdes[1]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT68[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.618</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT72[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT72[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_2/tmds_serdes[2]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT72[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.618</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT11[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT11[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_1/tmds_serdes[0]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT11[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.618</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT7[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT7[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_0/tmds_serdes[2]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT7[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.613</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.947</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.947</td>
<td>1.375</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL3[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL3[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_1/tmds_serdes[1]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL3[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.917%; route: 3.876, 84.114%; tC2Q: 0.367, 7.969%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.584</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.918</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.918</td>
<td>1.346</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL9[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL9[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_0/tmds_serdes[1]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL9[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.967%; route: 3.847, 84.014%; tC2Q: 0.367, 8.019%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.579</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.913</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.913</td>
<td>1.341</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL14[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL14[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_1/tmds_serdes[2]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL14[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.976%; route: 3.842, 83.996%; tC2Q: 0.367, 8.028%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.571</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.906</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.335</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.906</td>
<td>1.334</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL12[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.588</td>
<td>0.588</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.588</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1.521</td>
<td>0.932</td>
<td>tCL</td>
<td>FF</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL12[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>1.486</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_0/tmds_serdes[0]</td>
</tr>
<tr>
<td>1.335</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL12[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.588</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.989%; route: 3.834, 83.970%; tC2Q: 0.367, 8.042%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.032</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.921</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT66[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.176</td>
<td>1.176</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.176</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>2.109</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>2.109</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT66[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>2.074</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_2/tmds_serdes[0]</td>
</tr>
<tr>
<td>1.921</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT66[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.032</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.921</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT68[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.176</td>
<td>1.176</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.176</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>2.109</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>2.109</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT68[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>2.074</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_2/tmds_serdes[1]</td>
</tr>
<tr>
<td>1.921</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT68[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.032</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.921</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT72[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.176</td>
<td>1.176</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.176</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>2.109</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>2.109</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT72[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>2.074</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_2/tmds_serdes[2]</td>
</tr>
<tr>
<td>1.921</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT72[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.032</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.921</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT11[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.176</td>
<td>1.176</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.176</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>2.109</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>2.109</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT11[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>2.074</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_1/tmds_serdes[0]</td>
</tr>
<tr>
<td>1.921</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT11[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.032</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.921</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT7[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.176</td>
<td>1.176</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.176</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>2.109</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>2.109</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT7[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>2.074</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_0/tmds_serdes[2]</td>
</tr>
<tr>
<td>1.921</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT7[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.026</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.947</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.921</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.947</td>
<td>1.375</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL3[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.176</td>
<td>1.176</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.176</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>2.109</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>2.109</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL3[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>2.074</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_1/tmds_serdes[1]</td>
</tr>
<tr>
<td>1.921</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL3[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.917%; route: 3.876, 84.114%; tC2Q: 0.367, 7.969%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.998</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.918</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.921</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.918</td>
<td>1.346</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL9[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.176</td>
<td>1.176</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.176</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>2.109</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>2.109</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL9[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>2.074</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_0/tmds_serdes[1]</td>
</tr>
<tr>
<td>1.921</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL9[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.967%; route: 3.847, 84.014%; tC2Q: 0.367, 8.019%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.993</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.913</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.921</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.913</td>
<td>1.341</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL14[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.176</td>
<td>1.176</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.176</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>2.109</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>2.109</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL14[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>2.074</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_1/tmds_serdes[2]</td>
</tr>
<tr>
<td>1.921</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL14[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.593</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.976%; route: 3.842, 83.996%; tC2Q: 0.367, 8.028%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.937</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.890</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT66[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.043</td>
<td>0.160</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT66[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]/PCLK</td>
</tr>
<tr>
<td>5.890</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT66[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.179</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.160, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.946</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.899</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT68[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.052</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT68[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]/PCLK</td>
</tr>
<tr>
<td>5.899</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT68[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.170</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.169, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.946</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.899</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT72[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.052</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT72[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]/PCLK</td>
</tr>
<tr>
<td>5.899</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT72[A]</td>
<td>svo_hdmi_inst_2/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.170</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.169, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.946</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.899</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT11[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.052</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT11[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]/PCLK</td>
</tr>
<tr>
<td>5.899</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT11[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.170</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.169, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.946</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.899</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.953</td>
<td>1.380</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT7[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.052</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT7[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]/PCLK</td>
</tr>
<tr>
<td>5.899</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT7[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.170</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.908%; route: 3.881, 84.132%; tC2Q: 0.367, 7.960%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.169, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.150</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.913</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.064</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.913</td>
<td>1.341</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL14[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.217</td>
<td>0.334</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL14[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]/PCLK</td>
</tr>
<tr>
<td>6.064</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL14[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.005</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.976%; route: 3.842, 83.996%; tC2Q: 0.367, 8.028%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.334, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.152</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.947</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.100</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.947</td>
<td>1.375</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL3[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_1/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.253</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL3[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]/PCLK</td>
</tr>
<tr>
<td>6.100</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL3[A]</td>
<td>svo_hdmi_inst_1/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.917%; route: 3.876, 84.114%; tC2Q: 0.367, 7.969%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.158</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.918</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.076</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.707</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>3.208</td>
<td>2.501</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>3.572</td>
<td>0.365</td>
<td>tINS</td>
<td>RF</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>4.918</td>
<td>1.346</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL9[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>5.882</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.229</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL9[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]/PCLK</td>
</tr>
<tr>
<td>6.076</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL9[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.007</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.882</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.340, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.365, 7.967%; route: 3.847, 84.014%; tC2Q: 0.367, 8.019%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.347, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.577</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.703</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[0][A]</td>
<td style=" font-weight:bold;">led_cnt_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.849</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[0][A]</td>
<td>led_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>100.884</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_7_s0</td>
</tr>
<tr>
<td>100.703</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C37[0][A]</td>
<td>led_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.685</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.545%; route: 0.174, 20.455%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.577</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.703</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[0][B]</td>
<td style=" font-weight:bold;">led_cnt_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.849</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[0][B]</td>
<td>led_cnt_8_s0/CLK</td>
</tr>
<tr>
<td>100.884</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_8_s0</td>
</tr>
<tr>
<td>100.703</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C37[0][B]</td>
<td>led_cnt_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.685</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.545%; route: 0.174, 20.455%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.577</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.703</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[1][A]</td>
<td style=" font-weight:bold;">led_cnt_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.849</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[1][A]</td>
<td>led_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>100.884</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_9_s0</td>
</tr>
<tr>
<td>100.703</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C37[1][A]</td>
<td>led_cnt_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.685</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.545%; route: 0.174, 20.455%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.577</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.703</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[1][B]</td>
<td style=" font-weight:bold;">led_cnt_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.849</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[1][B]</td>
<td>led_cnt_10_s0/CLK</td>
</tr>
<tr>
<td>100.884</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_10_s0</td>
</tr>
<tr>
<td>100.703</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C37[1][B]</td>
<td>led_cnt_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.685</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.545%; route: 0.174, 20.455%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.577</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.703</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[2][A]</td>
<td style=" font-weight:bold;">led_cnt_11_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.849</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[2][A]</td>
<td>led_cnt_11_s0/CLK</td>
</tr>
<tr>
<td>100.884</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_11_s0</td>
</tr>
<tr>
<td>100.703</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C37[2][A]</td>
<td>led_cnt_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.685</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.545%; route: 0.174, 20.455%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.577</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.703</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[2][B]</td>
<td style=" font-weight:bold;">led_cnt_12_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.849</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[2][B]</td>
<td>led_cnt_12_s0/CLK</td>
</tr>
<tr>
<td>100.884</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_12_s0</td>
</tr>
<tr>
<td>100.703</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C37[2][B]</td>
<td>led_cnt_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.685</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.545%; route: 0.174, 20.455%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[3][A]</td>
<td style=" font-weight:bold;">led_cnt_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[3][A]</td>
<td>led_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_0_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C36[3][A]</td>
<td>led_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[0][A]</td>
<td style=" font-weight:bold;">led_cnt_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[0][A]</td>
<td>led_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_1_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C36[0][A]</td>
<td>led_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[0][B]</td>
<td style=" font-weight:bold;">led_cnt_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[0][B]</td>
<td>led_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_2_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C36[0][B]</td>
<td>led_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[1][A]</td>
<td style=" font-weight:bold;">led_cnt_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[1][A]</td>
<td>led_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_3_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C36[1][A]</td>
<td>led_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[1][B]</td>
<td style=" font-weight:bold;">led_cnt_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[1][B]</td>
<td>led_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_4_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C36[1][B]</td>
<td>led_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[2][A]</td>
<td style=" font-weight:bold;">led_cnt_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[2][A]</td>
<td>led_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_5_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C36[2][A]</td>
<td>led_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[2][B]</td>
<td style=" font-weight:bold;">led_cnt_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C36[2][B]</td>
<td>led_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_6_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C36[2][B]</td>
<td>led_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[0][A]</td>
<td style=" font-weight:bold;">led_cnt_13_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[0][A]</td>
<td>led_cnt_13_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_13_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C38[0][A]</td>
<td>led_cnt_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[0][B]</td>
<td style=" font-weight:bold;">led_cnt_14_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[0][B]</td>
<td>led_cnt_14_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_14_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C38[0][B]</td>
<td>led_cnt_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][A]</td>
<td style=" font-weight:bold;">led_cnt_15_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][A]</td>
<td>led_cnt_15_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_15_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C38[1][A]</td>
<td>led_cnt_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][B]</td>
<td style=" font-weight:bold;">led_cnt_16_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][B]</td>
<td>led_cnt_16_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_16_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C38[1][B]</td>
<td>led_cnt_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[2][A]</td>
<td style=" font-weight:bold;">led_cnt_17_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[2][A]</td>
<td>led_cnt_17_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_17_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C38[2][A]</td>
<td>led_cnt_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.698</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[2][B]</td>
<td style=" font-weight:bold;">led_cnt_18_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[2][B]</td>
<td>led_cnt_18_s0/CLK</td>
</tr>
<tr>
<td>100.879</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_18_s0</td>
</tr>
<tr>
<td>100.698</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C38[2][B]</td>
<td>led_cnt_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.680</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[2][A]</td>
<td style=" font-weight:bold;">led_cnt_23_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.840</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[2][A]</td>
<td>led_cnt_23_s0/CLK</td>
</tr>
<tr>
<td>100.875</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_23_s0</td>
</tr>
<tr>
<td>100.693</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C39[2][A]</td>
<td>led_cnt_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.675</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.455%; route: 0.164, 19.545%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[0][A]</td>
<td style=" font-weight:bold;">led_cnt_19_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.840</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[0][A]</td>
<td>led_cnt_19_s0/CLK</td>
</tr>
<tr>
<td>100.875</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_19_s0</td>
</tr>
<tr>
<td>100.693</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C39[0][A]</td>
<td>led_cnt_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.675</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.455%; route: 0.164, 19.545%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[0][B]</td>
<td style=" font-weight:bold;">led_cnt_20_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.840</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[0][B]</td>
<td>led_cnt_20_s0/CLK</td>
</tr>
<tr>
<td>100.875</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_20_s0</td>
</tr>
<tr>
<td>100.693</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C39[0][B]</td>
<td>led_cnt_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.675</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.455%; route: 0.164, 19.545%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[1][A]</td>
<td style=" font-weight:bold;">led_cnt_21_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.840</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[1][A]</td>
<td>led_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>100.875</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_21_s0</td>
</tr>
<tr>
<td>100.693</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C39[1][A]</td>
<td>led_cnt_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.675</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.455%; route: 0.164, 19.545%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>101.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>100.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led_cnt_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_50:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>100.164</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>u_Reset_Sync/reset_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>100.333</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_3_s0/Q</td>
</tr>
<tr>
<td>100.429</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[3][B]</td>
<td>n36_s2/I3</td>
</tr>
<tr>
<td>100.607</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>199</td>
<td>R18C34[3][B]</td>
<td style=" background: #97FFFF;">n36_s2/F</td>
</tr>
<tr>
<td>101.280</td>
<td>0.673</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[1][B]</td>
<td style=" font-weight:bold;">led_cnt_22_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>100.000</td>
<td>100.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>100.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>100.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>100.840</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C39[1][B]</td>
<td>led_cnt_22_s0/CLK</td>
</tr>
<tr>
<td>100.875</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>led_cnt_22_s0</td>
</tr>
<tr>
<td>100.693</td>
<td>-0.181</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C39[1][B]</td>
<td>led_cnt_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.675</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.164, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 15.914%; route: 0.769, 68.925%; tC2Q: 0.169, 15.161%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.455%; route: 0.164, 19.545%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.727</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.847</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.120</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst_0/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1474</td>
<td>LEFTSIDE[0]</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.169</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][B]</td>
<td>svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.342</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C41[1][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_2/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.716</td>
<td>1.374</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C35[1][B]</td>
<td>svo_hdmi_inst_0/n107_s1/I1</td>
</tr>
<tr>
<td>2.020</td>
<td>0.305</td>
<td>tINS</td>
<td>RR</td>
<td>309</td>
<td>R27C35[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst_0/n107_s1/F</td>
</tr>
<tr>
<td>2.847</td>
<td>0.827</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL12[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst_0/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>0.932</td>
<td>0.932</td>
<td>tCL</td>
<td>RR</td>
<td>10</td>
<td>PLL_L[1]</td>
<td>Gowin_PLL_inst/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>0.932</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL12[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>0.967</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst_0/tmds_serdes[0]</td>
</tr>
<tr>
<td>1.120</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL12[A]</td>
<td>svo_hdmi_inst_0/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.763</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.169, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.305, 11.380%; route: 2.201, 82.168%; tC2Q: 0.173, 6.452%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>1.767</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>2.767</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>svo_hdmi_inst_2/svo_tcard/vdma_tdata_0_s135</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>3.286</td>
<td>0.345</td>
<td>tNET</td>
<td>FF</td>
<td>svo_hdmi_inst_2/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.054</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>svo_hdmi_inst_2/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>1.770</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>2.770</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>svo_hdmi_inst_2/svo_tcard/vdma_tdata_0_s135</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.349</td>
<td>0.349</td>
<td>tNET</td>
<td>RR</td>
<td>svo_hdmi_inst_2/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>3.118</td>
<td>0.177</td>
<td>tNET</td>
<td>FF</td>
<td>svo_hdmi_inst_2/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>1.772</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>2.772</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>svo_hdmi_inst_0/svo_tcard/vdma_tdata_0_s135</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>3.277</td>
<td>0.336</td>
<td>tNET</td>
<td>FF</td>
<td>svo_hdmi_inst_0/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.049</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>svo_hdmi_inst_0/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>1.772</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>2.772</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>svo_hdmi_inst_1/svo_tcard/vdma_tdata_0_s135</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>3.277</td>
<td>0.336</td>
<td>tNET</td>
<td>FF</td>
<td>svo_hdmi_inst_1/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.882</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>6.049</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>svo_hdmi_inst_1/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>1.774</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>2.774</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>svo_hdmi_inst_0/svo_tcard/vdma_tdata_0_s135</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>svo_hdmi_inst_0/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>3.114</td>
<td>0.173</td>
<td>tNET</td>
<td>FF</td>
<td>svo_hdmi_inst_0/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>1.774</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>2.774</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>svo_hdmi_inst_1/svo_tcard/vdma_tdata_0_s135</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.340</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>svo_hdmi_inst_1/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2.941</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Gowin_CLKDIV_inst/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>3.114</td>
<td>0.173</td>
<td>tNET</td>
<td>FF</td>
<td>svo_hdmi_inst_1/svo_tcard/vdma_tdata_0_s135/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.833</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk_50</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>led_cnt_21_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.013</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>led_cnt_21_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.846</td>
<td>0.169</td>
<td>tNET</td>
<td>FF</td>
<td>led_cnt_21_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.833</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk_50</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>led_cnt_19_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.013</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>led_cnt_19_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.846</td>
<td>0.169</td>
<td>tNET</td>
<td>FF</td>
<td>led_cnt_19_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.829</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk_50</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>led_cnt_15_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>led_cnt_15_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.851</td>
<td>0.173</td>
<td>tNET</td>
<td>FF</td>
<td>led_cnt_15_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.825</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk_50</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>led_cnt_7_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.031</td>
<td>0.349</td>
<td>tNET</td>
<td>RR</td>
<td>led_cnt_7_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk_50</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.856</td>
<td>0.178</td>
<td>tNET</td>
<td>FF</td>
<td>led_cnt_7_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>1474</td>
<td>clk_p</td>
<td>-7.573</td>
<td>0.506</td>
</tr>
<tr>
<td>309</td>
<td>n107_5</td>
<td>-3.618</td>
<td>1.655</td>
</tr>
<tr>
<td>199</td>
<td>n36_7</td>
<td>-0.784</td>
<td>2.198</td>
</tr>
<tr>
<td>96</td>
<td>pixel_fifo_rdaddr[2]</td>
<td>-0.698</td>
<td>1.730</td>
</tr>
<tr>
<td>96</td>
<td>pixel_fifo_rdaddr[2]</td>
<td>-0.605</td>
<td>1.524</td>
</tr>
<tr>
<td>96</td>
<td>pixel_fifo_rdaddr[2]</td>
<td>-2.659</td>
<td>1.939</td>
</tr>
<tr>
<td>67</td>
<td>vdma_tdata_0_636</td>
<td>-0.344</td>
<td>3.544</td>
</tr>
<tr>
<td>66</td>
<td>vdma_tdata_23_13</td>
<td>0.727</td>
<td>3.864</td>
</tr>
<tr>
<td>55</td>
<td>dout_buf2_0_21</td>
<td>-0.041</td>
<td>5.508</td>
</tr>
<tr>
<td>51</td>
<td>pixel_fifo_rdaddr[1]</td>
<td>-0.656</td>
<td>1.672</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R7C45</td>
<td>45.83%</td>
</tr>
<tr>
<td>R14C51</td>
<td>45.83%</td>
</tr>
<tr>
<td>R14C46</td>
<td>44.44%</td>
</tr>
<tr>
<td>R15C35</td>
<td>44.44%</td>
</tr>
<tr>
<td>R15C51</td>
<td>44.44%</td>
</tr>
<tr>
<td>R18C45</td>
<td>44.44%</td>
</tr>
<tr>
<td>R26C24</td>
<td>43.06%</td>
</tr>
<tr>
<td>R27C24</td>
<td>41.67%</td>
</tr>
<tr>
<td>R23C35</td>
<td>41.67%</td>
</tr>
<tr>
<td>R16C27</td>
<td>41.67%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {clk}]</td>
</tr>
<tr>
<td>TC_REPORT_MAX_FREQUENCY</td>
<td>Actived</td>
<td>report_max_frequency -mod_ins {Gowin_PLL_inst}</td>
</tr>
</table>
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